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DS90UB947-Q1: DS90UB947-Q1 and DS90UB941AS-Q1 LINK LOST

Part Number: DS90UB947-Q1
Other Parts Discussed in Thread: DS90UB941AS-Q1

We are working with DS90UB947-Q1 and DS90UB941AS-Q1 chips and mentioned that they have different descriptions in common registers. For example, register 0xC for DS90UB941AS-Q1 used more status BITS starting from bit 4:

BIT 4: LINK_LOST
LINK_LOST_P1 R 0h Link Lost Flag for selected port:
This bit indicates that loss of link has been detected. This register bit
will stay high until cleared using the CRC ERROR RESET in register
0x04.
If PORT1_SEL is set, this register indicates Port1 Status as
indicated.
BIT 5:  DPHY_ERROR R 0h OR of LANE_SYNC_ERROR and DPHY_LANE_ERROR from DSI
indirect registers. Will not clear on read.
In Dual DSI or Independent 2:2 modes, this bit will indicate an error
was detected on either DPHY input.
BIT 6: DSI_ERROR R 0h OR of DSI_FPD3_ERR, DSI_CMD_OVER, DSI_EOT_ERR,
DSI_READ_WOUT_BTA, and DSI_ERROR_DET from DSI indirect
registers. Will not clear on read.
In Dual DSI or Independent DSI to FPD-Link III modes, this bit will
indicate an error was detected on either DSI input.
BIT 7: RESERVED R 0h General Status Register
If PORT1_SEL is set, this register indicates Port1 Status as
indicated.
Reserved.
For DS90UB947-Q1 bits from 4th bit reserved. Please tell me, are bits starting from 4 planned to be used in DS90UB947-Q1 chips? If so, when; How to determine the LINK LOST status for DS90UB947-Q1?