Hello team,
I have a question about XIO2001.
There is a description in XIO2001 datasheet 9.2.1.2.1 PCI Bus Interface.
- The bridge supports external PCI bus clock sources. If an external clock is a system requirement, the external clock source is connected to the CLK terminal. The trace length relationship between the synchronous bus signals and the external clock signals that is previously described is still required to meet PCI bus setup and hold. For external clock mode, all seven CLKOUT[6:0] terminals can be disabled using the clock control register at offset D8h. Plus, the XIO2001 clock run feature must be disabled with external PCI bus clocks because there is no method of turning off external clocks.
Do you have more detailed information when we use external clock source for PCI Bus?, and do you have also reference schematic for the use case?
Best regards,
