DP83869HM: Can VDDIO be powered up in advance of VDDA2P5 and VDDA1P1

Hello Peter Woodruff

Thank you for the query. Please refer below the recommended sequence.

For two supply configuration, the recommendation is to power all supplies together. If that is not possible then the following power sequencing needs to be used.

Figure 115. Two Supply Sequence Diagram

Regards,

Sreenivasa

Hello Peter Woodruff

For two supply configuration, the recommendation is to power all supplies together. If that is not possible then the following power sequencing needs to be used. Please  Refer to the below diagram in the datasheet.

Figure 115. Two Supply Sequence Diagram.

Regards,

Sreenivasa

Thank you for reiterating the datasheet statement.

Datasheet table 101 t2 states the maximum of 50ms but the minimum is not specified at all implying there is no minimum.

Can t2 shown on datasheet Figure 115 be a negative number?

Regards,

Adam

Hello Adam,

Thank you for the reply.

The VDDIO timing is Measured with respect to start of VDDA2P5 and VDDA1P1. 

Regards,

Sreenivasa

Hello Sreenivasa, 

Can t2 shown on your snapshot above (datasheet Figure 115) be a negative number? NOTE: there is no minimum shown for t2 in the table. 

Best regards, 

Adam 

Hello Adam,

Thank you for the reply.

The VDDIO can come up along with the other supplies or after the other supplies. 

Could you please provide additional details on the use case you are looking at ?

Regards,

Sreenivasa

I intend to provide VDDIO=3v3 - I am trying to minimise number of separate power rails and simplify rails power-on sequence.

I am trying to understand if VDDIO=3v3 can come up before VDDA2P5 and VDDA1P1.

Thank you

Hello Adam 

I am trying to understand if VDDIO=3v3 can come up before VDDA2P5 and VDDA1P1.

Do you have some measurement numbers? Is the delay in few us ?

Regards,

Sreenivasa

Hello Adam 

Do you have some input.

Regards,

Sreenivasa

Hi Sreenivasa, 

We were keen to power up VDDIO=3v3 20ms before VDDA2P5 and VDDA1P1.

Thank you for looking into it.

Adam

Hello Adam 

Thank you for providing the timing. Let me check and update on the feasibility.

Regards,

Sreenivasa

Hello Adam ,

Wishing  you a happy new year. I hope you had good holidays.

Would the 1P1 be available before 2P5 in the supply architecture that you are considering.

 Regards,

Sreenivasa

Hi Sreenivasa,

Happy new year. Currently will intend to enable 1P1 and 2P5 in exactly the same moment with exactly the same rise time.

Is VDDIO=3v3 20ms before 1P1 and then followed by 2P5 be allowed power on sequence? 

Regards

Adam

Hello Adam, 

Thank you for the reply.

Is VDDIO=3v3 20ms before 1P1 and then followed by 2P5 be allowed power on sequence? 

This would be a preferred sequence than both 1P1 and 2P5 coming together.

Would you be able to sequence the supply as above.

Regards,

Sreenivasa

HI Sreenivasa,

So VDDIO=3v3 can/is allowed to come up 20ms before 1P1 and 2P5 coming up together?

Best regards,

Adam 

Hello Adam, 

Thank you for the reply.

Design wanted to be sure 1.1 was not the last supply and hence i was checking with you.

Let me confirm with the design team on the sequence and come back to you.

Regards,

Sreenivasa

Hello Adam, 

hank you for waiting.

Below is the input i received from design

So VDDIO=3v3 can/is allowed to come up 20ms before 1P1 and 2P5.

It is recommended that the 1.1V ramps before the 2.5V.

Please let me know if you have any additional questions. If not please click the resolved button to close the thread. 

Regards,

Sreenivasa

Hi Sreenivasa, 

Above answer gives all information I need.

Thank you very much.

Adam

Hello Adam, 

Thank you. Please click the resolved button if you do not have additional questions.

Regards,

Sreenivasa