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DS90UB962-Q1: Drop of End of Frame

Ryan Wang
Expert 7475 points
Part Number: DS90UB962-Q1

Dear expert,

My system is UB935-UB962-SoC . According to "7.5.10 Error Handling" of datasheet, UB962 stop sending the CSI-2 frame in error condition which cause "downstream CSI-2 input receives a repeated Start of Frame". My customer own SoC will hang up for miss of  End of Frame( during ESD test). 

Then we clear 0x7C register PORT_CONFIG2 to 0 to clear bit 5 DISCARD_ON_PAR_ERR which is enabled by default. But SoC still hang up even more frequently.

Then we clear 0x02 register RX_PARITY_CHECKER_EN, then hang up disappear.

Questions are:

1. With clear 0x7C PORT_CONFIG2 to 0, UB962 send whole package with error, right? Why it seems doesn't take effect?

2. Is there any other register can disable either UB935 or UB962 to drop error packet?

3. With 0x02 register RX_PARITY_CHECKER_EN clear to 0, not only SoC doesn't hang up. There is also no screen blink. (Previously, screen blink during ESD test) It seems UB962 screen some good packet. Could you comment on this?

Thanks

  • 0
    TI__Expert 6345 points

    Hello Ryan,

    Please allow me a couple days to look into you questions. 

    Thank you,

    Best Regards,

    Shruti

  • 0
    TI__Expert 6345 points

    Hello Ryan,

    Yes, if bit DISCARD_ON_PAR_ERR = 0 the 962 will forward packets with parity errors. However, if there are any other errors like in line or frame size, the data will get forwarded. The settings in registers PORT_CONFIG2 (Table 7-139) and PORT_PASS_CTL (Table 7-140) control how the DS90UB962-Q1 handles errors when passing video frames. What are your settings for the PORT_PASS_CTL Register (Address 0x7D) and the PORT_CONFIG2 Register (Address 0x7C)?

    "The Pass indication may be used to prevent forwarding packets to the internal video buffers by setting the PASS_DISCARD_EN bit in the PORT_PASS_CTL register. When this bit is set, video input will be discarded until the Pass signal indicates valid receive data. The Receive port will indicate Pass status once specific conditions are met, including a number of valid frames received. Valid frames may include requiring no FPD-Link III Parity errors and consistent frame size, including video line length and/or number of video lines." "The Rx Port PASS indication may be used to prevent forwarding packets to the internal video buffers by setting the PASS_DISCARD_EN bit. When this bit is set, video input will be discarded until the Pass signal indicates valid receive data."

    When you clear 0x02 register RX_PARITY_CHECKER_EN to 0, the 962 doesn't check for any parity errors, so the frames are forwarded regardless of whether they have a parity error. Maybe there is a tolerance that your system/ISP can handle if it receives frames with parity errors. During the ESD test, some bits must be getting flipped or dropped, so there must have been an error condition preventing the forwarding of packets to the internal video buffers or the CSI-2 TX ports; thus the ISP is not receiving any CSI-2 data and the screen blinks. 

    Best Regards,

    Shruti

  • 0 in reply to Shruti More
    TI__Expert 7475 points

    Shruti,

    Thanks for detailed explanation. I will further check