SN65DSI83: Propagation delay

Hi,

Register 0x28 and 0x29 are CHA_SYNC_DELAY_HIGH and CHA_SYNC_DELAY_LOW. The field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for channel A. The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI83 device. The additional delay is approximately 10 pixel clocks. The sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. 

Thanks

David

Hello David-san,

Thank you for your reply.
Let me confirm way of idea about these registers.

For example, User set 0x28 and 0x29 set as shown below.
0x28 : 0x20
0x29 : 0x01
(This setting is same setting as datasheet of 8.2.2.1 example script)

Total delay should be calculated as shown below, right ?

* 288 pixel (0x120)+ 10 pixel = 298pixel clock

And, is my understanding that shortest delay case is as shown below correct ?

* 32pixel(0x20) + 10 pixel = 42pixel clock

How user estimate which value is better for their system ?
(In general, shortest delay is preffer. but I believe that there is case that user can not set this.)

Best Regards,

Hi,

The calculation looks correct. The best way is to measure the timing duration between the HSS on the DSI side and the HSYNC on the LVDS side.

Thanks

David