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DS90C387A: LVDS Display half screen problem

Part Number: DS90C387A
Other Parts Discussed in Thread: TFP401A-Q1, , TFP401A

Hi TI team,

Before we have a problem sharpness and pixel shift. Now we have fixed this problem with changed some resistor on hardware. But we have currently some problems too. After this hardware changing we tried different types edid files. But most of them we get half screen display and display does not fit on the screen. I have attached below our screen photo. Our video source is a PC's HDMI out. Then HDMI connects to HDMI-DVI converter so converter's DVI side plug to our board. Our display is Innolux M215HGE.

We generate edid file with https://github.com/akatrevorjay/edid-generator software on raspberry pi (Raspbian OS)

Our current edid configuration file at software is : 

/* EDID */

#define VERSION 1

#define REVISION 3

 

/* Display */

#define CLOCK 742500 /* kHz */

#define XPIX 1920

#define YPIX 1080

#define XY_RATIO XY_RATIO_16_9

#define XBLANK 45

#define YBLANK 140

#define XOFFSET 45

#define XPULSE 22

#define YOFFSET (140)

#define YPULSE (10+5)

#define DPI 96

#define VFREQ 60 /* Hz */

#define TIMING_NAME "Linux FHD"

/* No ESTABLISHED_TIMINGx_BITS */

#define HSYNC_POL 0

#define VSYNC_POL 0

 

#include "edid.S"

 We get a edid.bin file from software. We convert to hex format and burn the eeprom with https://github.com/tomka/write-edid software. Our last edid is (This edid used display on the attached photo)  :

 

$ hexdump –C edid.hex

00000000  00 ff ff ff ff ff ff 00  31 d8 00 00 00 00 00 00  |........1.......|

00000010  05 16 01 03 6d 32 1c 78  ea 5e c0 a4 59 4a 98 25  |....m2.x.^..YJ.%|

00000020  20 50 54 00 00 00 d1 c0  01 01 01 01 01 01 01 01  | PT.............|

00000030  01 01 01 01 01 01 0a 22  80 2d 70 38 8c 40 2d 16  |.......".-p8.@-.|

00000040  a0 00 f4 19 11 00 00 30  00 00 00 ff 00 4c 69 6e  |.......0.....Lin|

00000050  75 78 20 23 30 0a 20 20  20 20 00 00 00 fd 00 3b  |ux #0.    .....;|

00000060  3d 78 7a 4b 00 0a 20 20  20 20 20 20 00 00 00 fc  |=xzK..      ....|

00000070  00 4c 69 6e 75 78 20 46  48 44 0a 20 20 20 00 ce  |.Linux FHD.   ..|

00000080

Now we get half screen display with this configuration. Can you check and help us.

Thanks,

Berat Yıldız

  • Berat,

    The pixel clock in your timing is 1/2 of what it should be. This is a FHD 60Hz panel so you should be using 148.5MHz PCLK instead of 74.25MHz. The timing spec for the panel gives all the horizontal timing in 1/2 of the full panel timing since this is a dual OLDI panel. 

    It looks like a FHD 60Hz EDID dataset already exists in the Github that you linked: https://github.com/akatrevorjay/edid-generator/blob/master/1920x1080.S 

    Best Regards,

    Casey 

  • Hi Mr.Casey, thanks for your response. I have already tried original 1920x1080.S file which has 148,5Mhz frequency but result is same that screen seems half display. Also for be sure I have tried again. Also chips which we used are 

    TFP401A-Q1

    DS90C387A

    24C02 EEPROM (edid)

  • Hello Berat,

    When you plug this display, what does the PC recognize as the display resolution in the monitor properties? Please confirm on the PC side that the display is recognized as a 1080p monitor with 148.5MHz PCLK. You may need to adjust the display settings on the PC side in case there are multiple supported resolutions. 

    Please also double confirm the EDID that is generated because when I look at the one from your previous post it is identifying the incorrect PCLK rate in the timing descriptor:

    Best Regards,

    Casey 

  • Hi Casey,

    I generate again with original 1920x1080@60 edid and burn eeprom. Then we plugged to PC and we have seen same half screen. I attach my last edid, configration file and screenshots of pc's monitor information.

    /*
       1920x1080.S: EDID data set for standard 1920x1080 60 Hz monitor
    
       Copyright (C) 2012 Carsten Emde <C.Emde@osadl.org>
    
       This program is free software; you can redistribute it and/or
       modify it under the terms of the GNU General Public License
       as published by the Free Software Foundation; either version 2
       of the License, or (at your option) any later version.
    
       This program is distributed in the hope that it will be useful,
       but WITHOUT ANY WARRANTY; without even the implied warranty of
       MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
       GNU General Public License for more details.
    
       You should have received a copy of the GNU General Public License
       along with this program; if not, write to the Free Software
       Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA.
    */
    
    /* EDID */
    #define VERSION 1
    #define REVISION 3
    
    /* Display */
    #define CLOCK 148500 /* kHz */
    #define XPIX 1920
    #define YPIX 1080
    #define XY_RATIO XY_RATIO_16_9
    #define XBLANK 280
    #define YBLANK 45
    #define XOFFSET 88
    #define XPULSE 44
    #define YOFFSET (63+4)
    #define YPULSE (63+5)
    #define DPI 96
    #define VFREQ 60 /* Hz */
    #define TIMING_NAME "Linux FHD"
    /* No ESTABLISHED_TIMINGx_BITS */
    #define HSYNC_POL 1
    #define VSYNC_POL 1
    
    #include "edid.S"
    

         0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
    00: 00 ff ff ff ff ff ff 00 31 d8 00 00 00 00 00 00    ........1?......
    10: 05 16 01 03 6d 32 1c 78 ea 5e c0 a4 59 4a 98 25    ????m2?x?^??YJ?%
    20: 20 50 54 00 00 00 d1 c0 01 01 01 01 01 01 01 01     PT...??????????
    30: 01 01 01 01 01 01 02 3a 80 18 71 38 2d 40 58 2c    ???????:??q8-@X,
    40: 45 00 f4 19 11 00 00 1e 00 00 00 9f 00 4c 69 6e    E.???..?...?.Lin
    50: 75 78 20 23 30 0a 20 20 20 20 00 00 00 fd 00 3b    ux #0?    ...?.;
    60: 3d 42 44 0f 00 0a 20 20 20 20 20 20 00 00 00 fc    =BD?.?      ...?
    70: 00 4c 69 6e 75 78 20 46 48 44 0a 20 20 20 00 05    .Linux FHD?   .?
    80: 02 03 22 71 49 90 20 05 04 03 02 07 06 01 23 09    ??"qI? ???????#?
    90: 07 01 83 01 00 00 e3 05 03 01 67 03 0c 00 10 00    ????..????g??.?.
    a0: b8 2d 01 1d 80 18 71 1c 16 20 58 2c 25 00 34 cc    ?-????q?? X,%.4?
    b0: 31 00 00 9e 01 1d 00 72 51 d0 1e 20 6e 28 55 00    1..???.rQ?? n(U.
    c0: 34 cc 31 00 00 1e 8c 0a d0 8a 20 e0 2d 10 10 3e    4?1..????? ?-??>
    d0: 96 00 67 cc 21 00 00 18 8c 0a a0 14 51 f0 16 00    ?.g?!..?????Q??.
    e0: 26 7c 43 00 67 cc 21 00 00 ff 00 00 00 00 00 00    &|C.g?!.........
    f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3b    ...............;
    

  • Also I want to add more detail about hardware.

    We changed configure on TFP401A-Q1 via PIXS pin.

    When we set PIXS pin to GND -> we get half screen like before I attached photo.

    When we set PIXS pin to HIGH -> we get full screen but with pixel shift. Display not seems good. I attachted pictures below when PIXS pin is HIGH.

  • Berat,

    What mode are you using on the DS90C387A DUAL pin? Make sure PIXS is high on the TFP401A and DUAL is high on the DS90C387A to do DVI -> dual RGB -> dual OLDI which is what you would need for this PCLK rate 

    Best Regards,

    Casey 

  • Hi Casey,

    I attached our configration section at schematic, Can you check?

    Also we check now that PIXS and DUAL are high. We detect 74.5 MHZ at ODCK pin via scope. But our screen seems same as I attached photo before.

  • Berat,

    Do you see 74MHz at both output clocks on the DS90C387A? Are both LVDS channels connected to the panel?

    Best Regards,

    Casey 

  • Hi Casey,

    Yes the both LVDS channels are connected to panel. We can see 74Mhz at output clocks but clocks are not stable. Sometimes bounce to 68 mhz sometimes we see 80mhz etc. I attached video. 

  • Hey Berat,

    I suspect that your even/odd channels going to the panel are flipped somewhere in the signal chain which is why the panel looks full screen but still not correct in your previous pictures where PIXS is high. Basically you are getting the even/odd pixel orders backwards which is why you see artifacts like the gray line on the border with a white line in-between:

    Either the even/odd are flipped going from TFP401A to DS90C387A or the even/odd are flipped going from DS90C387A to the panel 

    Best Regards,

    Casey 

  • Hi Casey,

    You hit the point. we mixed up even/odd connection. Now display is pretty great. Thank you for your support. You are the best.