TCAN1145-Q1: Detection of "TXD Dominant Time Out" by software

Hi Taki,

There is no register value to directly detect dominant timeout. However, this can be determined indirectly by correlating the TXD output of the controller and the corresponding RXD state. If TXD is driven dominant (logic low), we always expect the received signal on RXD to also be low. Exceptions should only occur when the transceiver is unable to drive the bus or has experienced dominant timeout. Keep in mind this only applies to the dominant state as it is common for the TXD signal to be recessive (high) and the received data to be either recessive or dominant. 

Let me know if you have any more questions.

Regards,
Eric Schott