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XIO2001 PCIe to PCI Bridge

Chad Graham
Prodigy 10 points
Other Parts Discussed in Thread: XIO2001

I am implementing a XIO2001 bridge chip into my design and I have a couple general questions.

 

1) What are the recommended PCI resistor pull-up values for the INT#, DEVSEL#, FRAME#, etc... signals?

2)  What is the VREG_PD33 signal and what difference does adding a pull-up verses a pull-down make?

3) It is recommended that a 50Ohm series resistor be use to connect CLKOUT_6 to the CLKIN pin.  Is it also recommended that a 50Ohm series resistor be used on the used clocks?  What about the unused clocks?  Should a pull-down of some value be added to prevent the unused clock from adding noise into the circuit?

4) For confirmation, the combined power pins are not to be connected to the power rails supplying the device.  Only bypass caps are to be added.

 

Thanks in advance!

  • 0
    TI__Guru* 76130 points

    Hello Chad,

    We are reviewing your inquiry and will reply to you soon.

    Regards.

     

  • 0 in reply to Elias Villegas M.
    TI__Guru* 76130 points

    Hello Chad, find my answers below:

     

    1) A 10K pull-up will be fine for all of these signals.

    2) VREG_PD33 is the internal voltage regulator enable for 3.3V and must be tied directly to ground or by a 10K pull-down.

    3) A 50 ohm series resistor on CLKOUT[5:0] is not a requirement, but can be used in order to reduce circuit board EMI. Unused CLKOUTs can be left floating and disabled by asserting the appropriate CLOCK_DISABLE bit in the clock control register at offset D8h.

    4) That is correct, only capacitors are connected.

     

    Regards.