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DP83867E: Design Review

Subbulakshmi P
Prodigy 30 points
Part Number: DP83867E

Hi TI team,

Please review the attached schematic.
/cfs-file/__key/communityserver-discussions-components-files/138/SCH_5F00_TI_5F00_ETH_5F00_RGMII-_2800_1_2900_.pdf

  • 0
    TI__Mastermind 39855 points

    Hello,

    Schematic reviews typically take a 5 working day turnaround. I will look to have feedback by CoB 12/15/21/

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 30 points

    Hi  Gerome,
    Kindly do this schematic review on priority basis, as we are running out of time.

    Thanks in advance.

  • 0 in reply to Subbulakshmi P
    TI__Mastermind 39855 points

    Hello,

    The earliest I can pull to give a commit date would be 12/13/21. Would this work with your timeline?

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 30 points

    Hi Gerome,
    Can you please pull the date to 12/11/21?
    It will be okay for us.

  • 0 in reply to Subbulakshmi P
    TI__Mastermind 39855 points

    Hello,

    I can check if that is possible on my side, but in case, I would expect 12/13/21 latest in case.

    Sincerely,

    Gerome

  • +1 in reply to Gerome Cacho
    TI__Mastermind 39855 points

    Hello,

    My feedback:

    - Add another 10nF/1uF network on VDD1P0 rail

    - Ensure VDD1P8 pins are not shorted together

    - Change GND isolation capacitor to 4.7nF and DNP varistor

    - Ensure XTAL load caps are appropriate per xtal datasheet

    - Does NM mean "Not mounted"? Ensure that MDC is not pulled up.

    - No need to double up on center tap decoupling on PHY side. Single 100nF per center tap is sufficient

    - Strapping:

    + Address 5

    + Please change RX_CTRL and GPIO_0 Strapping. Currently mode 2. Unknown RX CLK Skew

    - 3.5ns TX Clk skew

    - SGMII enabled, mirror mode disabled

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 30 points

    Hi Gerome,

    Pleased find the my inline responses below,

    Add another 10nF/1uF network on VDD1P0 rail

    Response:--->>>  Added

    - Ensure VDD1P8 pins are not shorted together

    Response:---->>>  It is not shorted.

    - Change GND isolation capacitor to 4.7nF and DNP varistor

    Response:------>>> 4.7nF added and DNP Varistor added

    - Ensure XTAL load caps are appropriate per xtal datasheet

    Response:----->>> XTAL load cap are provided as per the datasheet recommendations.

    - Does NM mean "Not mounted"? Ensure that MDC is not pulled up.

    Response:----->>>> Yes, MDC is in DNP

    - No need to double up on center tap decoupling on PHY side. Single 100nF per center tap is sufficient

    Response:------->>>> Just provided for the safety purposes only, all are in DNP.

    - Strapping:

    + Address 5

    + Please change RX_CTRL and GPIO_0 Strapping. Currently mode 2. Unknown RX CLK Skew

    Response:- Strapping will be changed during board bring up time.

    - 3.5ns TX Clk skew

    - SGMII enabled, mirror mode disabled

    All your comments are addressed, Thanks for your valuable feedback @Gerome Thanks....