DP83867CR: DP83867CRRGM Porting issue with Qualcomm emac structure

Hi Gerome,

That's quite different as I got from that case.

As I know, the developer has been asked to use the driver that fits the kernel version.

That also confuses me lots. 

Hi Sam,

I apologize for the confusion. Let me check with the team regarding this issue. Please expect a response by Monday at latest.

Sincerely,
Gerome

Hi Gerome,

Thanks for helping us clarify this issue.

This issue is quite urgent.

Please kindly share the result with us once you have any news. 

Thanks,

Sam

Hi Gerome,

Thanks for sharing this great info. with me.

Here are some questions after merging this driver into my yocto project.

- How do I calculate the proper delay time of tx/rx clock?

- Do you have any experience if the driver failed at the emac can't find the PHY during the SoC boot up?

Thanks,

Sam

Hi Sam,

The only way to calibrate for proper skew times for RGMII would be to put the PHY in loopback mode and play around with the skew values until the communication is valid.

Regarding the driver, we have not seen that behavior.

Sincerely,

Gerome

Hi Gerome,

Thanks for the information.

The current issue I got is the SoC is not able to ping out and get IP via DHCP.

And I found the tx_clk and rx_clk are in different settings.

The rx_clk is 25MHz and the tx_clk is 125MHz.

Also, from the command(ethtool) on the SoC that shows the ethernet speed is 1000Mb/s.

Does this issue also cause by the clock delay?

Should the tx/rx_clk be set in the same clock skew?

If yes, then how?

Thanks,
Sam

Hi Sam,

The clocks should be the same. TX_CLK is driven by the MAC while RX_CLK is driven by the PHY. It sounds like the PHY is running up at 100Mbps while your MAC is expecting 1G functionality. What is the connection diagram of your design? Do you have 2 PHY's connected via MDI to complete ping? What is the cable used, Link Partner, and how often is this problem occurring (how many boards, how many LP)?

Sincerely,

Gerome

Hi Gerome,

The SoC (Qualcomm QCS610) connects to the DP83867 then the transformer to the RJ45 socket.

It should be only one PHY with this design.

The problem is always happening on our platform.

Also, let me clarify the clock define. 

The clock from PHY to SoC is 125MHz, and the clock from SoC to PHY is 25MHz.

Sorry, make that confused.

Is there any I can check on the hardware or read from the register to dig out the root cause?

This issue is bothering us for a long while and quite urgent.

Thanks,
Sam

Hi Sam,

Is there anything connecting the PHY to another PHY on the RJ-45? Do you have MDI link established? 

What is your intended link speed of the design?

Sincerely,

Gerome