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TL16C752CI-Q1: read and write access sequence and timing requirements

Nicolas PLUMEREL
Prodigy 160 points
Part Number: TL16C752CI-Q1

Hi,
we use a TL16C752CI-Q1 in an application and we have a doubt about how works the processor interface.
The figure 1 and 2 of the datasheet (Rev. A, which I assume is the latest revision available) show consecutive write accesses (figure 1) and read accesses (figure 2) respectively. In each figure, the first and second access sequence is different:
- the first access is controlled by an IORn or IOWn low pulse while the CSn signal is asserted
- whereas the second access is controlled by a CSn low pulse while the IORn (or IOWn) signal is asserted

I guess this implies that both types of accesses (IOWn/IORn controlled or CSn controlled) are supported by the device.
My understanding is therefore that any access begins when the last of CSn and IORn (or IOWn) goes low and ends when the first goes back high. In other words, the device detects
- the begining of an access when the logic OR of the IORn/IOWn and CSn signals goes low
- and the end of an access when the logic OR of those same signals goes high.
This makes sense considering the way the address setup and hold times (t6s and t6h) are represented.
    
If my understanding is correct, the timing requirements of the second access of figure 1 do not seem correctly represented as I would expect t16s and t16h to be referenced to the rising edge of CSn rather than the rising edge of IOWn. This would be consistent with the figure 2 by the way.
I would also expect t9d and t15d to be the minimum time between two valid accesses. So I would expect those timings to be represented from IORn or IOWn going high to CSn going low.
Can you please confirm that my understanding is correct and the errors in figure 1 & 2 ?

Kind regards,

Nicolas

  • 0
    Guru 316440 points

    This device is designed to be compatible with the ISA bus. A/D/IOWn/IORn are connected directly to the bus. The CSn signal is generated by address decoding logic on the add-on board; it might come earlier or later than IOWn/IORn, depending on how the decoder is implemented.
    (For more information about ISA signals and timings, see www.hardwarebook.info/ISA and www.bitsavers.org/pdf/intel/_busSpec/Intel_ISA_Spec2.01_Sep89.pdf.)

    The TL16C752CI-Q1 executes a write (i.e., D are latched into the internal register) on the rising edge of IOWn. It executes a read (i.e., D are driven to the register value) shortly after the falling edge of IORn or CSn, whichever comes later.

    If you are not using an ISA bus but are implementing the processor interface yourself, then you should simply assert and deassert the CSn and IOWn/IORn signals at the same time.

  • 0 in reply to Clemens Ladisch
    Prodigy 160 points

    Thank you Clemens for your answer.

    We don't use an ISA bus, we interface the TL16C752 with a microcontroller on a standalone board and the CSn is generated by an address decoding logic on the board (using a FPGA). The IOWn, IORn, address and data buses are directly connected to the microcontroller.

    Our microcontroller timings characteristics leads to a very short (few nanoseconds, not adjustable), address setup time with respect to IOW or IOR. As a consequence we have to implement a delay when generating the CSn selection signal (to ensure the required 10 ns setup time). This causes the CSn to go low after IORn/IOWn go low and also to return high after IORn/IOWn go high. Our access sequence is then a mix between the two accesses represented in figures 1 and 2: our sequence begins as starts the second access in the figures and ends like the closure of the first access in the figures.

    I understand that data bits are driven when IORn and CSn are both low and that the IORn or CSn edges can occur in any order both at the access opening and closure. It suggests that the data bus outputs are controlled through asynchronous logic combining the IORn and CSn signals.

    Regarding write accesses, I understand from your post that data are sampled/latched on the rising edge of IOWn even when CSn is high (as represented in figure 1) which seems very unusual. This leads me to wonder how the CSn signal is used by the device during write accesses. Any idea?

  • 0 in reply to Nicolas PLUMEREL
    TI__Guru 72161 points

    Hi Nicolas, 

    Nicolas PLUMEREL said:
    This causes the CSn to go low after IORn/IOWn go low and also to return high after IORn/IOWn go high.

    For the write timing, this doesn't make a difference since the writes get sampled during the rising #IOW, as long as both the #IOW and #CS are low for atleast t13w. 

    For reads, once both #CS and #IOR go low, the data should appear on the parallel D0-D7 lines after t12w. It doesn't care which signal goes high first. (I recall programing the D version of the device where when I wanted to do burst reads, I left #CS low and just toggled #IOR)

    So in your case, it shouldn't cause any issues.

    Any reason why you're using the C version of the device and not the D version?

    -Bobby