DP83867IS: SGMII clock behavior of the phy.

Dan Klepper

Prodigy 250 points

Part Number: DP83867IS

on the datasheet (page 5 - pin functions ) pin 33 - "SGMII COP" is declared as "driven by the PHY "

while its diff pair - pin 34 - "SGMII CON" is declared as "driven by the MAC".

both of them are noted as "outputs"

my first question is what should be the direction of the SGMII CLOCK ? I/O ?

if the answer is output - what should be the conditions (configuration ) in order to generate this clock output - (will STRAP configuration be sufficient? or must is be done via the SMI configuration ? )

regarding two additional input pins (27,28) SGMII_SIP/N - they are stated to be synchronous to the diff SGMII clock input - this stands in contradiction the definition of SGMII_COP/N which are noted as "Output" .

over 3 years ago

0 Kallikuppa Sreenivasa over 3 years ago

TI__Guru**** 190179 points

Hello Dan Klepper

Thank you for the query and your input. Appreciate your inputs.

Regarding Pin 33/34, the inputs are noted and the required updates will be made in the next revision.

Table 56. SGMII Control Register 1 (SGMIICTL1), Address 0x00D3

1 = 6-wire mode. Enable differential SGMII clock to MAC.

Regarding pin 27,28 let me check internally.

Regards,

Sreenivasa

+1 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 190179 points

Hello Dan Klepper

I have the below update.

In both 4 & 6 wire modes, SGMII interface internally recovers clock from data received on SGMII_SIP/N. There is no differential SGMII clock input to the PHY, so this data on SIP/N should be synchronous to MAC’s clock.

We will have this updated in the next datasheet release.

Regards,

Sreenivasa

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DP83867IS: SGMII clock behavior of the phy.