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TUSB8042A:About power-up, down sequence, clock input timing

user6236094
Intellectual 310 points
Part Number: TUSB8042A

TUSB8042Aの電源投入、クロック入力タイミング、パワーダウンシーケンスについて教えてください。
我々の回路構成は、水晶発振器(1.8V_CMOSを用いてXIの入力端子に入力するように構成されている。

【質問1】

データシートに「図 1 の電源投入タイミング要件」について質問があります。

GRSTzがコンデンサにGNDに接続されている場合、図1の「VDD→VDD33」のパワーアップシーケンスを満たす必要があります。

ただし、VDDとVDD33が安定した後にGRSTzがデサートされた場合、VDDとVDD33のパワーアップシーケンスを要求することなく、順不同で起動することは可能ですか?

(VDD→VDD33またはVDD33→VDDの順序)

[質問2]

VDDとVDD33が安定する前に、水晶発振器からXI端子にクロックを入力しても大丈夫ですか?

XI端末ですが、電源が供給されていない場合に入力を行うとラッチアップが発生しますか?

[質問3]

電源ダウンシーケンスについて教えてください。

電源を切る場合、XI端子の水晶発振器を停止した後、VDDとVDD33の電源を切ることをお勧めしますか?

  • 0
    TI__Guru 60870 points

    Hello,

    As long as 3.3V and 1.1V are ramping close together, there is no issue using the passive reset circuit. Since we were concerned about customer delaying the 1.1V ramp after
    the 3.3V ramp, the wording was added to the datasheet. The potential issue with 3.3V ramping before the 1.1V is that the passive reset circuit relies on the external
    capacitor and an internal pullup to 3.3V, if the 1.1V ramps well after the 3.3V ramp there is a chance the reset would end before the hub is fully powered.

    A 1uF capacitor on GRSTz is fine for most applications, but if the power supply ramp time is long, they may need to increase it to 2 uF to meet the power on reset
    timing conditions.

    Regards,

    JMMN

  • 0 in reply to JMMN
    Intellectual 310 points

    Hello,JMMN

    Thank you for your reply.
    I understand Question 1.

    Please tell me about Question 2 and Question 3.

    [Question 2]

    Is it okay to input the clock from the crystal oscillator to the XI terminal before VDD and VDD33 stabilize?

    [Question 3]
    Please tell me about the power down sequence.
    Is it okay to stop the 24MCLK (crystal oscillator) of the XI terminal after turning off the power of VDD and VDD33?

  • +1 in reply to user6236094
    TI__Guru 60870 points

    Functionally, having the clock start and stop after the device is powered on / off is ok, but the XI pin is not listed as fail-safe.

    Regards,

    JMMN