Hi Expert,
Our customer uses DP83TC811R-Q1 and the 100Base-T1 has failed. Test report is as below. Could you please provide some hint for debugging? Thanks a lot!
BR,
Elec Cheng
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi Expert,
Our customer uses DP83TC811R-Q1 and the 100Base-T1 has failed. Test report is as below. Could you please provide some hint for debugging? Thanks a lot!
BR,
Elec Cheng
Hello Elec,
Mode conversion is very sensitive measurement. It is dependent on the board layout and test-fixture.
Customer can try calibrating the test fixture (test fixture board + SMA cables etc) again and re-do the measurement. Otherwise trdp and trdm trace's length and environment matching will have to be improved.
--
Regards,
Vikram
Hi Vikram,
Do you have any report or application note that describes how to calibrating the test fixture? Do we have the test set-up pic? any instruction for performing the test? Our customer will perform the test again and they need these documents. That would be great if you can support. Thanks
BR,
Elec Cheng
Hi Vikram,
I attach some PCB layout pic and schematic. Please help review. Do you have an application called “PADS”. Our customer can provide PADS file. It's easier for reviewing. Thanks a lot for your efforts.
https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/PCB-layout-_2600_-schematic.7z
BR,
Elec Cheng
Hello Elec,
Customer needs to approach the test equipment vendor to know the details of required calibration.
--
Regards,
Vikram
We dont have PADS. I looked at the shared layout. Can they share the ground layer around/under the differential pair. They can also try removing ESD device and do the measurement (after calibration of fixture + SMA). Also make sure to use length matched SMA cables
--
Regards,
Vikram
Is this layout also showing ground layer just under the top layer (as requested)?
Just to be sure, I see full trdp and trdm traces (from PHY to connector )to be in top layer, without any vias. Is this correct?
What is the lenght mismatch of trdp and trdm traces (I dont see gross mismatch visually but maybe they can shared the lengths)?
They may try other suggestions also in previous email (ESD removal and calibration with matched SMA cables). That may help.