DP83867IR: MII loopback test failed

John11513

Part Number: DP83867IR
Other Parts Discussed in Thread: DP83867IS

Hi Experts:

My customer reported an issue with DP83867: It seems as if the PHY device cannot correctly receive the MAC data through RGMII interface.

They have done following test:

1. The link partner ping the questioned equipment, failed;

2. The questioned equipment can receive the data from link partner;

3. The questioned equipment cannot send data to link partner;

4. MII loopback test failed;

5. A-B-A test shows the issue follows the questioned device. (The questioned equipment resumes normal work once the questioned PHY device is replaced by a new one, and the good equipment cannot work anymore if the questioned device is soldered on it).

Should customer do further test before send the device for FA?

Thank you!

John

over 3 years ago

0 Kallikuppa Sreenivasa over 3 years ago

TI__Guru**** 189509 points

Hello John

Thank you for the query.

Could you please check with customer if the RGMII delay calibration has been considered.

RGMII Control Register (RGMIICTL), Address 0x0032

The default mode is align mode.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 189509 points

Hello John,

Additionally can you please ask customer to measure the trace length for the RGMII signals.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 189509 points

Hello John

Thank you for the query.

Could you please check with customer if the RGMII delay control has been considered.

RGMII Control Register (RGMIICTL), Address 0x0032

The default mode is align mode.

Additionally can you please ask customer to measure the trace length for the RGMII signals.

Is there a schematics to review ?

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 189509 points

Hello John

Is there a schematics to review ?

Regards,

Sreenivasa

0 John11513 over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Expert 5720 points

Hi Screenivasa,

The meaning of BIT 1 of Register 0x0032 is not clear to me. It says "1 = RGMII transmit clock is shifted relative to transmit data.". Does it means the BIT1 should be set to 1 if the clock has been shifted relative to transmit data externally? or it means the clock will be shifted on PHY device if this bit is set to 1?

In customer's design, the TX CLK (GTX) from MAC is aligned to transmit data, and the length of clock/data is about equal. Should the BIT 1 of 0x0032 be set to 0?

Thank you!

John

0 Kallikuppa Sreenivasa over 3 years ago in reply to John11513

TI__Guru**** 189509 points

Hello John

Thank you for the reply.

Is customer using 48 pin device or a pin device.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 189509 points

Hello John

Please expect delay in response due to year end holidays.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 189509 points

Hello John

Thank you for the reply.

Is customer using 48-pin device or a 64-pin device?

Regards,

Sreenivasa

0 John11513 over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Expert 5720 points

Hi Sreenivasa,

Thank you. It is 48pin device, DP83867IS.

Could you please answer my previous question? (about the meaning of BIT1 Register 0x0032H)

Regards,

John

+1 Kallikuppa Sreenivasa over 3 years ago in reply to John11513

TI__Guru**** 189509 points

Hello John,

Thank you for the reply.

The 8 pin has provision for delay control using pin strap of register.

Regarding Register 0X0032

By default, 0 = RGMII transmit clock is aligned to transmit data.

The delay can be changed by configuring bit to 1.

RGMII Transmit Clock Delay: 1 = RGMII transmit clock is shifted relative to transmit data.

The delay control is configured using the below register

RGMII Delay Control Register (RGMIIDCTL), Address 0x0086

Please refer to below section for additional details

8.4.1.1.2 1000-Mbps Mode Timing

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 189509 points

Hello John,

Please expect delay is response due to year end holidays.

Regards,

Sreenivasa

+1 Kallikuppa Sreenivasa over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 189509 points

Hello John,

The 48 pin has provision for delay control using pin strap or register.

Regards,

Sreenivasa

0 John11513 over 3 years ago in reply to Kallikuppa Sreenivasa

TI__Expert 5720 points

Hi Sreenivasa,

The transmit clock (GTX) is aligned to data at transmitter (MAC) side and the length of trace is matched so they configured BIT1 of 0x0032 register at '1', and configured register 0x0086 register at 0x68 (also tried 0xA8) to apply 1.75ns (or 2.75ns). Cannot fix the problem, MII loopback still failed.

We measured the impedance of MII pins. Found that GTX pin impedance significantly lower than good device. So we think the issue is due to GTX pin has been damaged. So let us close this case.

They reported anther problem with this part. I will post a new chat about this new issue.

Thank youi!

John

0 Kallikuppa Sreenivasa over 3 years ago in reply to John11513

TI__Guru**** 189509 points

Hello John,

Wishing you a happy new year 2022.

Thank you for the reply.

Please click the resolved button to clos the thread.

Regards,

Sreenivasa

+1 Kallikuppa Sreenivasa over 3 years ago in reply to John11513

TI__Guru**** 189509 points

Hello John,

Wishing you a happy new year 2022.

Thank you for the reply.

Please click the resolved button to clos the thread.

Regards,

Sreenivasa

Interface

Interface forum

DP83867IR: MII loopback test failed