SN65DSI86: tuning DSI Input

Markus Niebel

Part Number: SN65DSI86

We use the mentioned IC and having following Problem:

- Bridge uses external REFCLK

- Based on EDID data we can generate Test data by bridge and see it on display

- CPU side graphic stack is up and running

- Bridge Status says

STATUS REGISTERS:
[0xf0] = 0x00000003
[0xf1] = 0x00000000
[0xf2] = 0x00000000
[0xf3] = 0x00000000
[0xf4] = 0x00000000
[0xf5] = 0x00000000
[0xf6] = 0x00000000
[0xf7] = 0x00000000
[0xf8] = 0x00000000

No Picture on Display. No Output of HSYNC/VSYNC on GPIO2/3

Is there a AN how to use tuning options in register 0x11? Or should we look in different place for potential errors?

Thanks in advance

over 3 years ago

0 David (ASIC) Liu over 3 years ago

TI__Guru**** 176811 points

Hi,

Have you used the spreadsheet in this e2e guide to generate the DSI86 register programming value, https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945404/faq-sn65dsi86-how-do-i-programming-the-sn65dsi86-registers?

Thanks

David

0 Markus Niebel over 3 years ago in reply to David (ASIC) Liu

Prodigy 10 points

I use the mainline linux driver, because this is our use case. Since we can generate and display a test pattern based on EDID data from monitor we are sure to have a DP link to the monitor. On the input side of the bridge we see that images from the display controller are scanned out with the correct format and we observe signals over DSI lines.

0 David (ASIC) Liu over 3 years ago in reply to Markus Niebel

TI__Guru**** 176811 points

Hi,

Any chance you can share the schematic, the monitor EDID information, and the DSI86 registers programming value?

If you are not seeing HSYNC or VSYNC, the DSI video timing registers may not be programmed correctly.

Thanks

David

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SN65DSI86: tuning DSI Input