This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83869HM: DP83869 cannot correctly recognize the setting mode, and the network port cannot communicate

Part Number: DP83869HM
Other Parts Discussed in Thread: USB-2-MDIO, DP83869

Hi, support team

My customer has the questions as follow:

There is a problem at this stage: the network port does not respond after connecting to the network cable, the light on the LED does not light up, and there is no link up phenomenon.
Specific analysis:


1. After opening the putty serial debugging assistant, enter the u-boot debugging interface, and enter mii info, it will show that the register port corresponding to phy is 1000BASE-X, that is, the optical port, regardless of whether the network cable is connected or not.

Zynq> mii info
PHY 0x00: OUI = 0x80028, Model = 0x0F, Rev = 0x01, 1000baseX, HDX
PHY 0x08: OUI = 0x0000, Model = 0x00, Rev = 0x00, 10baseT, HDX

2. The configuration I added in the device tree is as follows:

#include <dt-bindings/net/ti-dp83869.h>
&gem1 {
gmii2rgmii-phy-handle = <&gmii_to_rgmii_0>;
phy-handle = <&phy1>;
ps7_ethernet_1_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: phy@1 {
reg = <0>;
device_type = "ethernet-phy";
tx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
rx-fifo-depth = <DP83869_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>;
ti,max-output-impedance = "true";
ti,clk-output-sel = <DP83869_CLK_O_SEL_CHN_A_RCLK>;
rx-internal-delay-ps = <2000>;
tx-internal-delay-ps = <2000>;
};
gmii_to_rgmii_0: phy@8{
compatible = "xlnx,gmii-to-rgmii-1.0";
device_type = "ethernet-phy";
phy-handle = <&phy1>;
reg = <8>;
};
};
};


If it is not configured in the device tree, the specific PHY chip cannot be identified, and the general-purpose phy is displayed when the kernel is started. In this case, enter the u-boot debugging interface and enter mii info and it still displays 1000BASE-X, but The network port can be identified, the LED light is on, and the boards can ping each other, but they cannot communicate with the PC.

3. I cannot read and write its registers through the USB-2-MDIO software, but I read and write through other methods. Respectively, read and write through the mdio read command under the u-boot debugging interface, and you can read the value of the general-purpose register; read and write by adding the printk command in the dp83869.c driver. The following are the register values ​​I have read. By comparing the manual, we can see that they are all correct register values. The RGMII-to-copper options I configured are also correct. Therefore, the 1000BASE-X situation should be an abnormal situation. Can I understand the reason why RJ45 cannot identify and communicate with each other?

0000-1140
0001-7949
0002-2000
0003-a0f1
0004-01e1
0005-0
0006-0064
0007-2001
0008-0
0009-0300
000a-0
000f-f000
0010-5048
0011-0002
DP83869_STRAP_STS1:0
DP83869_IO_MUX_CFG:c00
01df-DP83869_OP_MODE:40
MII_DP83869_PHYCTRL:5048
DP83869_CTRL:0
DP83869_RGMIICTL:0

It can be seen that the register information configuration required by RGMII-copper is correct. But I cannot be sure that the method of reading and writing I am using is completely correct.

4. Because I am using the petalinux2019.1 version of the system, its kernel version is version 4.19, and I only found the dp83869 driver adapted to the 4.14 version of the kernel in the reply on the official website. Did this cause my error?

My PUTTY startup information is as follows:

U-Boot 2019.01 (Dec 31 2021 - 08:38:35 +0000) Xilinx Zynq ZC702

CPU:   Zynq 7z020
Silicon: v3.1
Model: Zynq Zed Development Board
DRAM:  ECC disabled 512 MiB
MMC:   mmc@e0100000: 0
Loading Environment from SPI Flash... SF: Detected s25fl256s_64k with page size 256 Bytes, erase size 64 KiB, total 32 MiB
OK
In:    serial@e0001000
Out:   serial@e0001000
Err:   serial@e0001000
Model: Zynq Zed Development Board
Net:   ZYNQ GEM: e000c000, phyaddr 0, interface gmii
eth0: ethernet@e000c000
Hit any key to stop autoboot:  0
Device: mmc@e0100000
Manufacturer ID: 3
OEM: 5344
Name: SC16G
Bus Speed: 50000000
Mode : SD High Speed (50MHz)
Rd Block Len: 512
SD version 3.0
High Capacity: Yes
Capacity: 14.8 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
4174616 bytes read in 246 ms (16.2 MiB/s)
## Loading kernel from FIT Image at 10000000 ...
   Using 'conf@system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'kernel@1' kernel subimage
     Description:  Linux kernel
     Type:         Kernel Image
     Compression:  uncompressed
     Data Start:   0x100000f4
     Data Size:    4157088 Bytes = 4 MiB
     Architecture: ARM
     OS:           Linux
     Load Address: 0x00008000
     Entry Point:  0x00008000
     Hash algo:    sha1
     Hash value:   f84c4227be9a3c03c6798f14dfa1cb39ab8e30db
   Verifying Hash Integrity ... sha1+ OK
## Loading fdt from FIT Image at 10000000 ...
   Using 'conf@system-top.dtb' configuration
   Verifying Hash Integrity ... OK
   Trying 'fdt@system-top.dtb' fdt subimage
     Description:  Flattened Device Tree blob
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x103f7094
     Data Size:    15636 Bytes = 15.3 KiB
     Architecture: ARM
     Hash algo:    sha1
     Hash value:   918e2263cd9b3e1598a3d7409a8e7127bcdb1113
   Verifying Hash Integrity ... sha1+ OK
   Booting using the fdt blob at 0x103f7094
   Loading Kernel Image ... OK
   Loading Device Tree to 07ff9000, end 07fffd13 ... OK

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 4.19.0-xilinx (oe-user@oe-host) (gcc version 8.2.0 (GCC)) #1 SMP PREEMPT Fri Dec 31 08:01:27 UTC 2021
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: Zynq Zed Development Board
bootconsole [earlycon0] enabled
Memory policy: Data cache writealloc
cma: Reserved 16 MiB at 0x1f000000
random: get_random_bytes called from start_kernel+0x80/0x3c4 with crng_init=0
percpu: Embedded 16 pages/cpu @(ptrval) s35916 r8192 d21428 u65536
Built 1 zonelists, mobility grouping on.  Total pages: 130048
Kernel command line: console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 493120K/524288K available (6144K kernel code, 205K rwdata, 1616K rodata, 1024K init, 132K bss, 14784K reserved, 16384K cma-reserved, 0K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
    vmalloc : 0xe0800000 - 0xff800000   ( 496 MB)
    lowmem  : 0xc0000000 - 0xe0000000   ( 512 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0x(ptrval) - 0x(ptrval)   (7136 kB)
      .init : 0x(ptrval) - 0x(ptrval)   (1024 kB)
      .data : 0x(ptrval) - 0x(ptrval)   ( 206 kB)
       .bss : 0x(ptrval) - 0x(ptrval)   ( 133 kB)
rcu: Preemptible hierarchical RCU implementation.
rcu:    RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
        Tasks RCU enabled.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to (ptrval)
slcr mapped to (ptrval)
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
zynq_clock_init: clkc starts at (ptrval)
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
Switching to timer-based delay loop, resolution 3ns
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
timer #0 at (ptrval), irq=17
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
CPU0: Spectre v2: using BPIALL workaround
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100060
rcu: Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs ...
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
CPU1: Spectre v2: using BPIALL workaround
smp: Brought up 1 node, 2 CPUs
SMP: Total of 2 processors activated (1333.33 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes)
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor menu
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x(ptrval)
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 25, base_baud = 6249999) is a xu`▒▒k▒▒▒▒[ttyPS0] enabled
console [ttyPS0] enabled
bootconsole [earlycon0] disabled
bootconsole [earlycon0] disabled
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
media: Linux media interface: v0.10
videodev: Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
FPGA manager framework
Advanced Linux Sound Architecture Driver Initialized.
clocksource: Switched to clocksource arm_global_timer
NET: Registered protocol family 2
tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
TCP established hash table entries: 4096 (order: 2, 16384 bytes)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
UDP hash table entries: 256 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: no interrupt-affinity property for /pmu@f8891000, guessing.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
workingset: timestamp_bits=30 max_order=17 bucket_order=0
jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
io scheduler mq-deadline registered
io scheduler kyber registered
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
brd: module loaded
loop: module loaded
m25p80 spi0.0: found s25fl256s1, expected n25q512a
m25p80 spi0.0: s25fl256s1 (32768 Kbytes)
4 fixed-partitions partitions found on MTD device spi0.0
Creating 4 MTD partitions on "spi0.0":
0x000000000000-0x000000500000 : "boot"
0x000000500000-0x000000520000 : "bootenv"
0x000000520000-0x000000fa0000 : "kernel"
0x000000fa0000-0x000002000000 : "spare"
libphy: Fixed MDIO Bus: probed
CAN device driver interface
libphy: MACB_mii_bus: probed
DP83869_STRAP_STS1:0
DP83869_IO_MUX_CFG:c00
DP83869_OP_MODE:40
MII_DP83869_PHYCTRL:5048
DP83869_CTRL:0
DP83869_RGMIICTL:0
TI DP83869 e000c000.ethernet-ffffffff:00: attached PHY driver [TI DP83869] (mii_bus:phy_addr=e000c000.ethernet-ffffffff:00, irq=POLL)
macb e000c000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000c000 irq 27 (00:0a:35:00:22:02)
e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
usbcore: registered new interface driver usb-storage
chipidea-usb2 e0002000.usb: e0002000.usb supply vbus not found, using dummy regulator
chipidea-usb2 e0002000.usb: Linked as a consumer to regulator.0
ULPI transceiver vendor/product ID 0x0451/0x1507
Found TI TUSB1210 ULPI transceiver.
ULPI integrity check: passed.
ci_hdrc ci_hdrc.0: EHCI Host Controller
ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
i2c /dev entries driver
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer at (ptrval) with timeout 10s
EDAC MC: ECC not enabled
Xilinx Zynq CpuIdle Driver started
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
mmc0: SDHCI controller on e0100000.mmc [e0100000.mmc] using ADMA
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
NET: Registered protocol family 10
Segment Routing with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered protocol family 17
can: controller area network core (rev 20170425 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20170425)
can: broadcast manager protocol (rev 20170425 t)
can: netlink gateway (rev 20170425) max_hops=1
Registering SWP/SWPB emulation handler
of-fpga-region fpga-full: FPGA Region probed
hctosys: unable to open rtc device (rtc0)
of_cfs_init
of_cfs_init: OK
ALSA device list:
  No soundcards found.
Waiting for root device /dev/mmcblk0p2...
mmc0: new high speed SDHC card at address aaaa
mmcblk0: mmc0:aaaa SC16G 14.8 GiB
 mmcblk0: p1 p2
EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
VFS: Mounted root (ext4 filesystem) on device 179:2.
devtmpfs: mounted
Freeing unused kernel memory: 1024K
Run /sbin/init as init process
INIT: version 2.88 booting
random: fast init done
Starting udev
udevd[747]: starting version 3.2.5
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
udevd[748]: starting eudev-3.2.5
ha1588: loading out-of-tree module taints kernel.
The major of the test device is 244
remap_size is 4096
res->start is 41000000
ha1588probed at VA 0xe0988000
FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
hwclock: can't open '/dev/misc/rtc': No such file or directory
Fri Dec 31 08:38:59 UTC 2021
hwclock: can't open '/dev/misc/rtc': No such file or directory
urandom_read: 2 callbacks suppressed
random: dd: uninitialized urandom read (512 bytes read)
mknod: /deb/dp83869: No such file or directory
Hello PetaLinux World
INIT: Entering runlevel: 5
Configuring network interfaces... IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
done.
Starting Dropbear SSH server: random: dropbear: uninitialized urandom read (32 bytes read)
dropbear.
hwclock: can't open '/dev/misc/rtc': No such file or directory
Starting internet superserver: inetd.
Starting syslogd/klogd: done
Starting tcf-agent: OK

PetaLinux 2019.1 wr_2 /dev/ttyPS0
wr_2 login: root
Password:
root@wr_2:~# ifconfig
eth0      Link encap:Ethernet  HWaddr 00:0A:35:00:22:02
          inet addr:192.168.0.100  Bcast:0.0.0.0  Mask:255.255.255.0
          UP BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)
          Interrupt:27 Base address:0xc000

lo        Link encap:Local Loopback
          inet addr:127.0.0.1  Mask:255.0.0.0
          inet6 addr: ::1/128 Scope:Host
          UP LOOPBACK RUNNING  MTU:65536  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)

Thanks so much.

Best regards,
Yuki

  • Here is the driver file:

    // SPDX-License-Identifier: GPL-2.0
    /* Driver for the Texas Instruments DP83869 PHY
     * Copyright (C) 2019 Texas Instruments Inc.
     */
    
    #include <linux/ethtool.h>
    #include <linux/kernel.h>
    #include <linux/mii.h>
    #include <linux/module.h>
    #include <linux/of.h>
    #include <linux/phy.h>
    #include <linux/delay.h>
    
    #include <dt-bindings/net/ti-dp83869.h>
    
    #define DP83869_PHY_ID		0x2000a0f1
    #define DP83869_DEVADDR		0x1f
    
    #define MII_DP83869_PHYCTRL	0x10
    #define MII_DP83869_MICR	0x12
    #define MII_DP83869_ISR		0x13
    #define DP83869_CTRL		0x1f
    #define DP83869_CFG4		0x1e
    
    /* Extended Registers */
    #define DP83869_GEN_CFG3        0x0031
    #define DP83869_RGMIICTL	0x0032
    #define DP83869_STRAP_STS1	0x006e
    #define DP83869_RGMIIDCTL	0x0086
    #define DP83869_IO_MUX_CFG	0x0170
    #define DP83869_OP_MODE		0x01df
    #define DP83869_FX_CTRL		0x0c00
    
    #define DP83869_SW_RESET	BIT(15)
    #define DP83869_SW_RESTART	BIT(14)
    
    /* MICR Interrupt bits */
    #define MII_DP83869_MICR_AN_ERR_INT_EN		BIT(15)
    #define MII_DP83869_MICR_SPEED_CHNG_INT_EN	BIT(14)
    #define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN	BIT(13)
    #define MII_DP83869_MICR_PAGE_RXD_INT_EN	BIT(12)
    #define MII_DP83869_MICR_AUTONEG_COMP_INT_EN	BIT(11)
    #define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN	BIT(10)
    #define MII_DP83869_MICR_FALSE_CARRIER_INT_EN	BIT(8)
    #define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN	BIT(4)
    #define MII_DP83869_MICR_WOL_INT_EN		BIT(3)
    #define MII_DP83869_MICR_XGMII_ERR_INT_EN	BIT(2)
    #define MII_DP83869_MICR_POL_CHNG_INT_EN	BIT(1)
    #define MII_DP83869_MICR_JABBER_INT_EN		BIT(0)
    
    #define MII_DP83869_BMCR_DEFAULT	(BMCR_ANENABLE | \
    					 BMCR_FULLDPLX | \
    					 BMCR_SPEED1000)
    
    /* This is the same bit mask as the BMCR so re-use the BMCR default */
    #define DP83869_FX_CTRL_DEFAULT	MII_DP83869_BMCR_DEFAULT
    
    /* CFG1 bits */
    #define DP83869_CFG1_DEFAULT	(ADVERTISE_1000HALF | \
    				 ADVERTISE_1000FULL | \
    				 CTL1000_AS_MASTER)
    
    /* RGMIICTL bits */
    #define DP83869_RGMII_TX_CLK_DELAY_EN		BIT(1)
    #define DP83869_RGMII_RX_CLK_DELAY_EN		BIT(0)
    
    /* STRAP_STS1 bits */
    #define DP83869_STRAP_STS1_RESERVED		BIT(11)
    #define DP83869_STRAP_MIRROR_ENABLED           BIT(12)
    
    /* PHYCTRL bits */
    #define DP83869_RX_FIFO_SHIFT	12
    #define DP83869_TX_FIFO_SHIFT	14
    
    /* PHY_CTRL lower bytes 0x48 are declared as reserved */
    #define DP83869_PHY_CTRL_DEFAULT	0x48
    #define DP83869_PHYCR_FIFO_DEPTH_MASK	GENMASK(15, 12)
    #define DP83869_PHYCR_RESERVED_MASK	BIT(11)
    
    /* RGMIIDCTL bits */
    #define DP83869_RGMII_TX_CLK_DELAY_SHIFT	4
    
    /* IO_MUX_CFG bits */
    #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL	0x1f
    
    #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX	0x0
    #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN	0x1f
    #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK	(0x1f << 8)
    #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT	8
    
    /* CFG3 bits */
    #define DP83869_CFG3_PORT_MIRROR_EN              BIT(0)
    
    /* CFG4 bits */
    #define DP83869_INT_OE	BIT(7)
    
    /* OP MODE */
    #define DP83869_OP_MODE_MII			BIT(5)
    #define DP83869_SGMII_RGMII_BRIDGE		BIT(6)
    
    enum {
    	DP83869_PORT_MIRRORING_KEEP,
    	DP83869_PORT_MIRRORING_EN,
    	DP83869_PORT_MIRRORING_DIS,
    };
    
    struct dp83869_private {
    	int tx_fifo_depth;
    	int rx_fifo_depth;
    	int io_impedance;
    	int port_mirroring;
    	bool rxctrl_strap_quirk;
    	int clk_output_sel;
    	int mode;
    };
    
    static int dp83869_ack_interrupt(struct phy_device *phydev)
    {
    	int err = phy_read(phydev, MII_DP83869_ISR);
    
    	if (err < 0)
    		return err;
    
    	return 0;
    }
    
    static int dp83869_config_intr(struct phy_device *phydev)
    {
    	int micr_status = 0;
    
    	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
    		micr_status = phy_read(phydev, MII_DP83869_MICR);
    		if (micr_status < 0)
    			return micr_status;
    
    		micr_status |=
    			(MII_DP83869_MICR_AN_ERR_INT_EN |
    			MII_DP83869_MICR_SPEED_CHNG_INT_EN |
    			MII_DP83869_MICR_AUTONEG_COMP_INT_EN |
    			MII_DP83869_MICR_LINK_STS_CHNG_INT_EN |
    			MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN |
    			MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN);
    
    		return phy_write(phydev, MII_DP83869_MICR, micr_status);
    	}
    
    	return phy_write(phydev, MII_DP83869_MICR, micr_status);
    }
    
    static int dp83869_config_port_mirroring(struct phy_device *phydev)
    {
    	struct dp83869_private *dp83869 = phydev->priv;
    	int val;
    
    	val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_GEN_CFG3);
    	if (val < 0)
    		return val;
    
    	if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN)
    		val |= DP83869_CFG3_PORT_MIRROR_EN;
    	else
    		val &= ~DP83869_CFG3_PORT_MIRROR_EN;
    
    	return phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_GEN_CFG3, val);
    }
    
    #if IS_ENABLED(CONFIG_OF_MDIO)
    static int dp83869_of_init(struct phy_device *phydev)
    {
    
    	struct dp83869_private *dp83869 = phydev->priv;
    	struct device *dev = &phydev->mdio.dev;
    	struct device_node *of_node = dev->of_node;
    	int ret;
    
    	if (!of_node)
    		return -ENODEV;
    
    	dp83869->io_impedance = -EINVAL;
    
    	/* Optional configuration */
    	ret = of_property_read_u32(of_node, "ti,clk-output-sel",
    				   &dp83869->clk_output_sel);
    	if (ret || dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK)
    		dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK;
    
    	ret = of_property_read_u32(of_node, "ti,op-mode", &dp83869->mode);
    	if (ret == 0) {
    		if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
    		    dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
    			return -EINVAL;
    	}
    
    	if (of_property_read_bool(of_node, "ti,max-output-impedance"))
    		dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX;
    	else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
    		dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN;
    
    	if (of_property_read_bool(of_node, "enet-phy-lane-swap")) {
    		dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
    	} else {
    		/* If the lane swap is not in the DT then check the straps */
    		ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
    		printk("DP83869_STRAP_STS1:%lx\n",ret);
    		if (ret < 0)
    			return ret;
    		
    		if (ret & DP83869_STRAP_MIRROR_ENABLED)
    			dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
    		else
    			dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS;
    
    		ret = 0;
    	}
    
    	if (of_property_read_u32(of_node, "rx-fifo-depth",
    				 &dp83869->rx_fifo_depth))
    		dp83869->rx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
    
    	if (of_property_read_u32(of_node, "tx-fifo-depth",
    				 &dp83869->tx_fifo_depth))
    		dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
    
    	return 0;
    }
    #else
    static int dp83869_of_init(struct phy_device *phydev)
    {
    	return 0;
    }
    #endif /* CONFIG_OF_MDIO */
    
    static int dp83869_configure_rgmii(struct phy_device *phydev,
    				   struct dp83869_private *dp83869)
    {
    	int ret, val;
    
    	if (phy_interface_is_rgmii(phydev)) {
    		val = phy_read(phydev, MII_DP83869_PHYCTRL);
    		if (val < 0)
    			return val;
    
    		val &= ~DP83869_PHYCR_FIFO_DEPTH_MASK;
    		val |= (dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT);
    		val |= (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT);
    
    		ret = phy_write(phydev, MII_DP83869_PHYCTRL, val);
    		if (ret)
    			return ret;
    	}
    
    	if (dp83869->io_impedance >= 0) {
    		val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG);
    		if (val < 0)
    			return val;
    
    		val &= ~DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
    		val |= dp83869->io_impedance &
    			       DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
    		printk("DP83869_IO_MUX_CFG:%lx\n",val);
    		ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG, val);
    		if (ret)
    			return ret;
    	}
    
    	return 0;
    }
    
    static int dp83869_configure_mode(struct phy_device *phydev,
    				  struct dp83869_private *dp83869)
    {
    	int phy_ctrl_val;
    	int val;
    	int ret;
    
    	if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
    	    dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
    		return -EINVAL;
    
    	/* Below init sequence for each operational mode is defined in
    	 * section 9.4.8 of the datasheet.
    	 */
    	ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
    			    dp83869->mode);
    	if (ret)
    		return ret;
    
    	ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT);
    	if (ret)
    		return ret;
    
    	phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT |
    			dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT |
    			DP83869_PHY_CTRL_DEFAULT);
    
    	switch (dp83869->mode) {
    	case DP83869_RGMII_COPPER_ETHERNET:
    		ret = phy_write(phydev, MII_DP83869_PHYCTRL,
    				phy_ctrl_val);
    		if (ret)
    			return ret;
    
    		ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
    		if (ret)
    			return ret;
    
    		ret = dp83869_configure_rgmii(phydev, dp83869);
    		if (ret)
    			return ret;
    		break;
    	case DP83869_RGMII_SGMII_BRIDGE:
    		val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE);
    		if (val < 0)
    			return val;
    
    		val |= DP83869_SGMII_RGMII_BRIDGE;
    		ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, val);
    		if (ret)
    			return ret;
    
    		ret = phy_write_mmd(phydev, DP83869_DEVADDR,
    				    DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
    		if (ret)
    			return ret;
    
    		break;
    	case DP83869_1000M_MEDIA_CONVERT:
    		ret = phy_write(phydev, MII_DP83869_PHYCTRL,
    				phy_ctrl_val);
    		if (ret)
    			return ret;
    
    		ret = phy_write_mmd(phydev, DP83869_DEVADDR,
    				    DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
    		if (ret)
    			return ret;
    		break;
    	case DP83869_100M_MEDIA_CONVERT:
    		ret = phy_write(phydev, MII_DP83869_PHYCTRL,
    				phy_ctrl_val);
    		if (ret)
    			return ret;
    		break;
    	case DP83869_SGMII_COPPER_ETHERNET:
    		ret = phy_write(phydev, MII_DP83869_PHYCTRL,
    				phy_ctrl_val);
    		if (ret)
    			return ret;
    
    		ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
    		if (ret)
    			return ret;
    
    		ret = phy_write_mmd(phydev, DP83869_DEVADDR,
    				    DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
    		if (ret)
    			return ret;
    
    		break;
    	case DP83869_RGMII_1000_BASE:
    	case DP83869_RGMII_100_BASE:
    		break;
    	default:
    		return -EINVAL;
    	}
    
    	return 0;
    }
    
    static int dp83869_config_init(struct phy_device *phydev)
    {
    	struct dp83869_private *dp83869 = phydev->priv;
    	int ret, val;
    
    	ret = dp83869_configure_mode(phydev, dp83869);
    	if (ret)
    		return ret;
    
    	/* Enable Interrupt output INT_OE in CFG4 register */
    	if (phy_interrupt_is_valid(phydev)) {
    		val = phy_read(phydev, DP83869_CFG4);
    		val |= DP83869_INT_OE;
    		phy_write(phydev, DP83869_CFG4, val);
    	}
    
    	if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP)
    		dp83869_config_port_mirroring(phydev);
    
    	/* Clock output selection if muxing property is set */
    	if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) {
    		val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG);
    		if (val < 0)
    			return val;
    
    		val &= ~DP83869_IO_MUX_CFG_CLK_O_SEL_MASK;
    		val |= dp83869->clk_output_sel <<
    		       DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT;
    
    		ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG, val);
    		if (ret)
    			return ret;
    	}
    
    	return 0;
    }
    
    static int dp83869_probe(struct phy_device *phydev)
    {
    	struct dp83869_private *dp83869;
    	int ret;
    
    	dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869),
    			       GFP_KERNEL);
    	if (!dp83869)
    		return -ENOMEM;
    
    	phydev->priv = dp83869;
    
    	ret = dp83869_of_init(phydev);
    	if (ret)
    		return ret;
    
    	return dp83869_config_init(phydev);
    }
    
    static int dp83869_phy_reset(struct phy_device *phydev)
    {
    	int ret;
    
    	ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET);
    	if (ret < 0)
    		return ret;
    
    	int read1 = phy_read_mmd(phydev,DP83869_DEVADDR,DP83869_OP_MODE);
    	int read2 = phy_read(phydev, MII_DP83869_PHYCTRL);
    	int read4 = phy_read(phydev, DP83869_CTRL);
    	int read5 = phy_read(phydev, DP83869_RGMIICTL);
    	printk("DP83869_OP_MODE:%lx\n",read1);
    	printk("MII_DP83869_PHYCTRL:%lx\n",read2);
    	printk("DP83869_CTRL:%lx\n",read4);
    	printk("DP83869_RGMIICTL:%lx\n",read5);
    
    	usleep_range(10, 20);
    
    	/* Global sw reset sets all registers to default.
    	 * Need to set the registers in the PHY to the right config.
    	 */
    	return dp83869_config_init(phydev);
    }
    
    static struct phy_driver dp83869_driver[] = {
    	{
    		.name		= "TI DP83869",
    		.phy_id		= DP83869_PHY_ID,
    		.phy_id_mask	= 0xfffffff0,
    
    		.probe          = dp83869_probe,
    		.config_init	= dp83869_config_init,
    		.soft_reset	= dp83869_phy_reset,
    
    		/* IRQ related */
    		.ack_interrupt	= dp83869_ack_interrupt,
    		.config_intr	= dp83869_config_intr,
    
    		.suspend	= genphy_suspend,
    		.resume		= genphy_resume,
    	},
    };
    module_phy_driver(dp83869_driver);
    
    static struct mdio_device_id __maybe_unused dp83869_tbl[] = {
    	{ DP83869_PHY_ID, 0xfffffff0 },
    	{ }
    };
    MODULE_DEVICE_TABLE(mdio, dp83869_tbl);
    
    MODULE_DESCRIPTION("Texas Instruments DP83869 PHY driver");
    MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
    MODULE_LICENSE("GPL v2");
    

  • Hello,

     Usually strap resistors are used on the board to configure device in the required mode at boot-up. Customer may check the schematic once to make sure that correct strap setting is under use for PHY to boot-up in required mode. We are not sure about the u-boot OS requirements and the required updates required in the sample linux driver, hence may not be directly identify the root-cause of the issue. But customer may try following software configuration to force the PHY in Rgmii-Copper mode (from datasheet section 9.4.8)

    "After configuring register 0x01DF, perform the following operations.
    • Write 0x1140 to register 0x0000
    • Write 0x5048 to register 0x0010
    • Write 0x0B00 to register 0x0009"

    --

    Regards,

    Vikram

  • Hello,

    Regarding the strap information, I make sure that I configure it correctly. I will configure the JTAG_EDO, RX_D3, and RX_D2 of its functional mode to be set to 0. As can be seen from the register information I gave above, 0x6E STRAP_STS is 0 , Indicating that the strap configuration is correct. Similarly, the registers I gave above can also indicate that I have performed the following operations
    • Write 0x1140 to register 0x0000
    • Write 0x5048 to register 0x0010
    • Write 0x0B00 to register 0x0009"
    But it did not succeed in making me recognize the Ethernet port. Do I have other methods to verify where is the problem?

    Best regards

  • Hello Qi,

    I will check with team once but from present data I am not able to root-cause the issue. May be you can try enabling loopback and see if you see the link-up(after removing the cable).

    reg    data

    01DF 0040 //to enable rgmii to copper mode
    00FE E720
    0000 0140
    0010 5008
    0016 0008
    001F 4000

    Read register 0001 for the link-up status.

    --

    Regards,

    Vikram