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DS90UB953-Q1: Data Diagnostics (CRC and Parity)

Justin Bohr
Mastermind 27980 points
Part Number: DS90UB953-Q1

Hi Team,

I am trying to clarify each of the CRC and Parity checks and associated registers when using the 953/954 combo.

I have segmented the CRC/Parity register per data path/type below with some questions. Please correct any identification errors.

BCC:

  • 953:
    • CRC_ERR_EN (0x1E)
      • Enable CRC_ERR alarm
    • CRC_ERR (0x52)
      • BCC CRC error detected
    • CRC_ERR_CLR (0x49)
      • BCC CRC Error clear
    • RX_PARTIY_CHECKER_ENABLE (953 0x32)
      • BCC Parity check enable?
  • 954
    • BC_CRC _GENERATOR _ENABLE (0x58)
      • BCC CRC generator enable
      BCC_CRC_ERROR (0x4D)
      • BCC error detected
    • BCC_ALARM (0x51) 
      • Alarm flag for back channel error from serializer
    • IE_BCC_CRC_ERR (0xD8)
      • Interrupt on BCC CRC error detect
  • Questions:
    • If there is a CRC error on the BCC, will the 953 stop any I2C transactions from going to its I2C bus?
    • The default for the 954 BC_CRC_GENERATOR_ENABLE is enabled.
      • Is there any register that needs to be written on the 953 side to enable BCC CRC error checking?
      • If you disable the CRC generator, will the 953 automatically recognize there is no CRC and transmit all I2C to its I2C bus from the BCC (permitting that the I2C/alias settings are correct)?
    • Is BCC_SEQ_ERROR related to a CRC/Checksum or parity error?
    • Is RX_PARITY_CHECKER_ENABLE a parity check for the received BCC frame?
      • If so, this is confusing as the 954 has the same named feature/register bit but for the forward channel, and there is no explanation on the 953 datasheet for it.
      • I don't see a register setting in the 954 to enable/disable BCC parity bit, is it always on?

Forward Channel:

  • 953
    • CRC_TX_GEN_ ENABLE (0x02)
      • Enable/Disable Forward Channel CRC?
  • 954
    • RX_PARITY_CHECKER_ENABLE (954 0x02)
      • FPD-Link III Parity Checker Enable
    • PARITY_ERROR (0x4D)
      • FPD-Link III parity errors detected
    • FPD3_ENC_CRC_DIS (0xBA)
      • Enable/Disable FPD-Link III encoder CRC
    • FPD3_ENC_CRC_CAP (0x4A)
      • Enable/Disable CRC error flag from FPD-Link III encoder
  • Questions:
    • In the 954 datasheet it talks about the RX_PARITY_CHECKER being related to the "received FPD-Link III frame". To me that says the 954 received the frame, and its the forward frame parity. Is the RX_PARITY_CHECKER_ENABLE in the 953 the same parity or is it a separate parity for the BCC? 
      • Is there a need to enable the forward channel parity on the 953 side?
    • Is CRC_TX_GEN_ ENABLE a CRC generated for the full forward channel frame (CSI-2 + control + I2C) by the 953?
      • Is the the CRC that the FPD3_ENC_CRC_DIS setting is dealing with?

CSI-2:

  • 953
    • CSI_CHKSUM_ERR_EN (0x1C)
      • CSI-2 Checksum Error Alarm Enable
    • CSI_ERR_CNT (0x5C)
      • CSI-2 Error Counter Register
    • CHKSUM_ERR (0x5D)
      • Indicates a checksum error detected in the incoming data (uncorrectable).
  • 954
    • CSI_CHKSUM_ERR (0x54)
      • CSI-2 checksum error from serializer
    • CSI_FWD_CKSUM (0x6D)
      • Forward CSI packets with checksum errors
    • CKSUM_ERR (0x7A)
      • Data Checksum Error detected for received CSI packet
  • Questions:
    • Is the CSI_CHKSUM_ERR_EN considered the enable/disable for the 953 to calculate and check the CSI-2 frame CRC?

BIST:

  • 953
    • BIST_CRC_ERR
    • BIST_CRC_ERR_ CLR
    • BIST_BC_ ERRCNT
    • CRC_ERR_CNT1/CRC_ERR_CNT2 ?
    • CHKSUM_ERR
  • 954

DCA:

  • 953
    • DCA_CRC_EN (0x33)
      • DCA CRC Enable
  • Questions:
    • I don't see any mention of a DCA CRC in the 954, is it utilized by the 954?

Thanks,

Justin Bohr

  • 0
    TI__Guru** 107510 points

    Hello Justin,

    Justin Bohr said:
    RX_PARTIY_CHECKER_ENABLE (953 0x32)
    • BCC Parity check enable?

    This bit enables the parity check function. This allows detection of errors on the FPD3 receiver data bits.
    Parity check is for the whole frame not just the BCC.

    • Questions:
      • If there is a CRC error on the BCC, will the 953 stop any I2C transactions from going to its I2C bus? The 953 will not stop any I2C transaction, but due to the CRC error it is possible that the I2C command reachs the 953 wrong or reaches a wrong device (e.g. an error alters I2C address)
      • The default for the 954 BC_CRC_GENERATOR_ENABLE is enabled.
        • Is there any register that needs to be written on the 953 side to enable BCC CRC error checking? Yes, 0x32[3]. But this is enabled by default.
        • If you disable the CRC generator, will the 953 automatically recognize there is no CRC and transmit all I2C to its I2C bus from the BCC (permitting that the I2C/alias settings are correct)? Yes, if you disable the back channel CRC generating on the deserializer, the SER will not see any CRC error. But that does not mean the communication will be error free. you may have errors on the back channel or on the BCC but these will not be detected by the SER. 
      • Is BCC_SEQ_ERROR related to a CRC/Checksum or parity error? The control channel commands are sent as packets over the forward channel link. The packets contain a 3-bit sequence number. If a packet is received with an unexpected sequence number, this error is flagged.  
      • Is RX_PARITY_CHECKER_ENABLE a parity check for the received BCC frame? 

        FPD-Link forward channel for 953 uses a 40 bit frames. Each frame should include an even number of 1s, and the 953 includes one parity bit into each frame in order to ensure this. A parity error happens if the DES finds that the received frame has an odd number of 1s

  • 0 in reply to Hamzeh Jaradat
    TI__Guru** 107510 points

    Forward channel Questions:

      • In the 954 datasheet it talks about the RX_PARITY_CHECKER being related to the "received FPD-Link III frame". To me that says the 954 received the frame, and its the forward frame parity. Is the RX_PARITY_CHECKER_ENABLE in the 953 the same parity or is it a separate parity for the BCC? This bit enables the CRC checker for the back channel.
        • Is there a need to enable the forward channel parity on the 953 side? You can't enable or disable parity generation.
      • Is CRC_TX_GEN_ ENABLE a CRC generated for the full forward channel frame (CSI-2 + control + I2C) by the 953?
        • Is the the CRC that the FPD3_ENC_CRC_DIS setting is dealing with?

    The CRC/Parity bit is generated to provide even parity of the 32-bit payload plus I2C and CSI mode indication bits.

    The 953 uses CRC to detect errors in the backchannel (DES -> SER) and the deserializer will check for parity errors in the forward channel (SER -> DES).  I2C is transferred over these channels however there is no direct error detection. Since the intention of the FPD-Link devices is to provide the appearance that the local and remote I2C buses are actually the same bus, we just recreate the I2C comms on either side.

    Additionally, I can send you a power point going through all these mechanisms.