Hi Team,
1. Do we have figure or diagram about SN65DSI83/84 test packet?
2. For 0x19 reg, does it mean that we can modify the CLK/DATA amplitude by this reg?
3. What is the meaning of 0x0A[7]?
Regards,
Roy
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Hi Team,
1. Do we have figure or diagram about SN65DSI83/84 test packet?
2. For 0x19 reg, does it mean that we can modify the CLK/DATA amplitude by this reg?
3. What is the meaning of 0x0A[7]?
Regards,
Roy
Roy
1. Do we have figure or diagram about SN65DSI83/84 test packet?
The DSI83/84 is sending out the color bar as the test packet
2. For 0x19 reg, does it mean that we can modify the CLK/DATA amplitude by this reg?
Correct, register 0x19 provides common mode and differential output voltage control
3. What is the meaning of 0x0A[7]?
You can treat this as a PLL lock indicator bit.
Thanks
David