I perform an experiment on 927+926 and I observe some weird test result. 926 can output lock high, that is great. But after that I can test around 31.02MHz clock on PCLK pin of 926. But I didn't even enable the patgen function. How does this happen? And when I enbale the patgen function from 927 side, the PCLK will change to the setting value. After I disable patgen from 927, the PCLK frequency will return to 31.02MHz. I test it several times and it happens all the time? Does it have some default PCLK output? Thanks for clarifying!