DS90UB927Q-Q1: 927+926 experiment

Part Number: DS90UB927Q-Q1

Hi Expert,

I perform an experiment on 927+926 and I observe some weird test result. 926 can output lock high, that is great. But after that I can test around 31.02MHz clock on PCLK pin of 926. But I didn't even enable the patgen function. How does this happen? And when I enbale the patgen function from 927 side, the PCLK will change to the setting value. After I disable patgen from 927, the PCLK frequency will return to 31.02MHz. I test it several times and it happens all the time?  Does it have some default PCLK output? Thanks for clarifying!

BR,

Elec Cheng

  • Hi Elec, 

    Just to verify your question, you are not seeing 31.02MHz when you actually send video across the link right? You are observing this only when there is no video being sent? 

    So there is no issue here, you are just curious why it is outputting 31.02MHz when no active video is being received? 

    Regards, 

    Logan

  • Hi Logan,

    Just to verify your question, you are not seeing 31.02MHz when you actually send video across the link right?---YES

    You are observing this only when there is no video being sent? ---Yes

    So there is no issue here, you are just curious why it is outputting 31.02MHz when no active video is being received? Yes

    BR,

    Elec Cheng

  • Hi Elec, 

    Thanks for confirming. I'm looking into this for you. I'll get back to you early next week. 

    Regards, 

    Logan

  • Hi Elec, 

    After looking into this, the below are potential reasons why you are seeing the 31.02MHz.

    92x des devices have a always-on/OSC clock output feature when lock is lost (maybe also when PCLK/video is not available on ser side), as described in register 0x2[5].

    Regards, 

    Logan