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Original question:
Hi, Ti
Currently our circuits are used when 947 and 948 are matched, However, the LOCK of the 948 is unstable and does not lock well, and the register configuration of the 948 cannot be written.
Considering that it may be caused by timing, what is their correct timing?
The timing we have set so far is as follows:
947 Power on→Pull up the PDB of the 947→948 Power on→Pull up the PDB of the 948→Configure the 947→Configure the 948
Is this timing correct?What is the correct time interval for each？
Hi Zhijian,
Please see the Recommended Power-Up Sequence diagram and table in the 947 and 948 datasheets for the required timings for power rails, PDB, and device to device interval times.
Let me know if you have any additional questions, and if still experience issues; then post power-up waveforms of both 947 and 948's VDD and PDB rails.
Regards,
Logan
