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DP83867IS: TMS320C6657 with DP83867IS connect failed

SEN LIN
Prodigy 20 points
Part Number: DP83867IS
Other Parts Discussed in Thread: TMS320C6657,

Hello, we are using tms320c6657 and DP83867 for ethernet circuit design and currently encountered the following problems:

We can access the registers of the PHY chip through MDIO, and can read the feedback value. Both the PHY register and the hardware LINK LED indicate that it links up.

However, when reading the DSP SGMII register and the EMAC register, it shows that the link is not successful. The same code can be debugged using the development board. The following is a comparison of the relevant registers of the development board and our own board.

  • 0
    TI__Mastermind 39785 points

    Hello,

    It seems like Link is successful (Reg 0x1[2] = '1'), correct?

    Can you confirm if SGMII is enabled with either strapping and/or register access?

    Can you confirm SGMII layout practices 9.2.2.1.1 are being followed?

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 20 points

    Thanks.

    1. We confirmed that Link is successful (Reg 0x1[2] = '1') ;

    2. Both Hardware starp and register can confirm that SGMII is ENABLE 

    Two more questions:

    3.could you tell me where can I find “SGMII layout practices 9.2.2.1.1 ”

    4.The EVM usePHY 88E1112,while  we use TI PHY DP83867.Are there any changes we should do when debug?

  • 0 in reply to SEN LIN
    TI__Mastermind 39785 points

    Hello,

    I am referring to section 9.2.2.1.1 in DP83867IS's datasheet. Can you confirm that these guidelines are being followed, and that AC coupling caps of 0.1uF are present on each line as seen in figures 14 and 15?

    Also to confirm, you are basing your design on an EVM which has 88E1112, but now will adjust with DP83867 as these are not pin-to-pin compatible?

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 20 points

    TI  FAE in  China has checked our hardware，AC coupling cap are present now and layout meets 9.2.2.1.1 rules.

    We have designed our PCB basing on EVM ,and changed PHY from 88E1112 to DP83867IS only. We confrm that the standard example code  can debug successfully on EVM,but failed when using our PCB. 

    Are there any changes should be done when Debug from 88E1112 to DP83867?

  • 0 in reply to SEN LIN
    TI__Mastermind 39785 points

    Hello,

    Can you expand on how the standard code debugged successfully on the EVM, but failed on the design?

    If TI FAE has checked your hardware, then there shouldn't be any more concerns with that. But to double check, can you please give me a register dump of 0x0 - 0x1F, 0x6E, 0x6F, 0x37?

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 20 points

    this  is the informaton tested yesterday:

    link is up，but SGMII Auto-neg failed.

  • 0 in reply to SEN LIN
    TI__Mastermind 39785 points

    Hi,

    The strapping looks okay, so from SW, this should be fine. How long are the SGMII traces? Also, I would like to take my own look of the schematic. Can you please upload? In terms of changes between parts, SNLA331 might suffice.

    Sincerely,

    Gerome