DP83849C: DP83849C vs DP83849I

Hi Gerome,

Thank you for your helpful information.

In addition, the datasheet of DP83849C doesn't have VledOL/OH(LED drive spec).

Is it same with DP83849I?

VledOL Output low voltage IOL = 2.5 mA  0.4V(MAX)

VledOH Output high voltage IOH = –2.5 mA Vcc – 0.5V(MIN)Best Regards,

Regards,

ttd 

Hi Gerome,

Thank you for your reply.

Did you check with the team about "CLK2MAC High/Low Time" and  "CLK2MAC propagation delay" and it was a typographical error?

If Both C grade and I grade are the same, which is the correct description on datahseet,?

■I grade 

   T2.31.1 CLK2MAC high/Low Time ⇒　10ns(Typ),8ns(max) for RMII mode

　T2.31.2 CLK2MAC propagation delay　⇒　blank

■C grade 

   T2.29.1 CLK2MAC High/Low Time ⇒ 10ns(Typ), max is blank for  RMII mode

　T2.29.2 CLK2MAC propagation delay　⇒　8ns

Best Regards,

ttd

Hi Gerome,

Thank you for your reply.

I understand that your comment is following and both I and C are same.

>This is a typo, where instead of 8ns max for CLK2MAC High/Low, this value is the typical for prop delay.

⇒By the way, prop delay of  C grade is 8ns(max). I grade is 8ns(typ)?

    Is it difference of 8ns(max) and 8ns(typ) between them?

■I grade 

Your answer: prop delay is 8ns(typ)

■C grade 

prop delay is 8ns(max)

Best Regards,

ttd

Hi Gerome,

DP83849C does not have the following specifications in the data sheet.

Q1 Is it only for SMII / SCMII communication?

Q2 Please tell us how the standard CLK was changed between I and C products.

Other question

Q3 Are DP83849C and DP83849I same die?

DP83849I

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SINGLE CLOCK MII (SMII) TRANSMIT TIMING

T2.28.1  X1 Clock Period

T2.28.2  TXD[3:0], TX_EN Data Setup

T2.28.3  TXD[3:0], TX_EN Data Hold

T2.28.4  X1 Clock to PMD Output Pair Latency (100Mb)

SINGLE CLOCK MII (SCMII) RECEIVE TIMING

T2.29.1  1 Clock Period

T2.29.2  RXD[3:0], RX_DV and RX_ER output delay

T2.29.3  CRS ON delay (100Mb)

T2.29.4  CRS OFF delay (100Mb)

T2.29.5  RXD[1:0] and RX_ER latency (100Mb)

---------------

Best Regards,

ttd