Hello sirs,
I'm planning to employ the TLK10081 for mux/demultiplexion or six Gigabit Ehternet channels in the same way as Application Report: SLLA347 but after reading througly the datasheet and the report I have some questions:
1. In SLLA347 the TLK10081 is configured in bit interleave mode. Does Clock Tolerance Compensation works with this configuration? (I understand it doestn't since the device can't aling to 10bit words in this mode)
2. The reference clock for both TLK10081 sides in SLLA347 block diagram seems to be the same. Whould the TLK10081 configured in this manner work properly for this application providing the reference clock for the two devices are different and consequenly not in phase?
3. What are the GIGE mode bits on transmit and receive path (register 1x1C LS_CH_CONTROL: bits 8,9)?
4. Lastly, if you can provide more information or advice for the Gigabit Ethernet agregation application it will be very welcome.
Best regards,
Jose.