Dear TI:
Please help check the proj design below:
SOC(455M DSICLK)->UB941->UB948->Display
SOC output is 148mhz PCLK. PCLK 75MHz can be found on ub948. About 75MHz DB exceeded the standard, resulting in EMC test failure. Can you check the problem for us?
BRs,
Zhaohui.Chen