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MDIO interface of TI TLK3138 XAUI Transceiver

Ravi Bemra
Prodigy 10 points

I'm unsure of the acceptable settings of the 5-bit-each pair of addresses DevID and PhyID needed by the MDIO header, for the TI TLK3138 transceiver.

On our EVB, I believe the DEVID[4:0] were left floating/NC while the PRTAD[4:0] pins were grounded.

I've exhaustively gone through all 32 x 32 combinations to read the part ID registers 0x2, 0x3, but always get back 0xFFFF.

Thanks!

 - Ravi

 

  • 0
    TI__Guru 62920 points

    Hi Ravi,

    The most significant 4 bits (bits 4:1) of the PHY Address portion of the MDIO header should correspond to the hardware configuration of the PRTAD[4:1] pins.  In your case, this would be 0000.  The least significant bit (bit 0) determines which XGXS is addressed.  XGXS A is addressed when this bit is 0 and XGXS B is addressed when this bit is 1.

    The most significant 4 bits (4:1) of the device ID are required to be 0010.  The least significant bit (bit 0) should correspond to the hardware configuration of the DEVID[0] pin, and determines whether a PHY device (bit 0 = 0) or DTE device (bit 0 = 1) is selected.  The DEVID[0] pin should have a pull-up or pull-down resistor installed on the application board so that its state is known.

    I hope this clears up any confusion.  Please let me know if you have any additional questions.

    Best regards,
    Max Robertson
    Analog Applications Engineer
    Texas Instruments
    m-robertson@ti.com