SN65DSI83: MIPI DSI-LVDS bridge input clock frequency

1.  Are you planning to use REFCLK or DSI CLK to the SN65DSI83?  The center spread CLK input to the REFCLK or DSI CLK is passed through to the LVDS CLK output A_CLKP and A_CLKN, or B_CLKP and B_CLKN, or both.  Section 7.3.1 of the datasheet explains how to configure the clock output:

2. Can you provide a block diagram of your system?  Max cable length will depend on the signal speed as well as amount of PCB trace / connectors.

Regards,

JMMN

Thanks Jamin for prompt response..!

As mentioned, We're using DSI CLK (DACP/DACN). Schematics screenshot attached below -

18-bits RGB format, DSI 4-lanes data, frame rate = 10 fps, Display resolution = 10” WXGA (1280x800) 

What will be DSI signal speed if LVDS clock speed is 69MHz?

Block Diagram:

Option-1:

LVDS data speed will be half of the DSI lane data speed as option-1 has 4-lanes

Option-2:

18-bits RGB format, DSI 2-lanes data, frame rate = 10 fps, Display resolution = 10” WXGA (1280x800) 

What will be DSI signal speed?

Hello,

We will review your question and respond by mid week.

Regards,

JMMN

Thanks JMMN, your response is much appreciated.