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DP83867IS: MDIO power up behavior

Kazuki Itoh
Genius 11130 points
Part Number: DP83867IS


Hi team,

My customer uses DP83867IS with Zynq FPGA.
They have similar two board (FPGA and PHY schematic is almost the same), but the the MDIO behavior at power up is different.
When right after power on, the board-A's MDIO stays high.
In the board B case, MDIO goes low 190ms after powering on, then go back to high after FPGA configuration.
Could you please let me know what triggers this behavior difference?

Regards,
Itoh

  • +1
    TI__Mastermind 26035 points

    Hi Kazuki,

    MDIO is an open drain line. The low level of the MDIO will be forced by FPGA or PHY and high level will be forced by pull up on the board. PHY does not control the MDIO line until asked by FPGA (during SMI transaction) hence in the present case if MDIO is observed to be going low in one of the board, it must be FPGA who is driving this low. Kindly check the FPGA behavior.

    Regards,

    Hillman Lin