Hello,
we are trying to get a 953 serializer design with an attached FPGA running.
The 953 is reporting for every lane that the sync pattern is incorrect, but we cannot find the cause and we have no oscilloscope to see the signals. The PCB must be correct since we got it running with another FPGA design.
In the datasheet I see several "reserved" registers close to the MIPI error registers.
Could you provide us the documentation for those registers if they will help debugging this problem?
Best regards, Juergen
