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SN65LVDT14: max rise time value for A/B inputs missing

Part Number: SN65LVDT14
Other Parts Discussed in Thread: SN65MLVD047, DS90LV011A

Hello,

I was wondering for the SN65LVDT14 IC, whether there is a maximum rise and fall time on A and B inputs during transition? Or are the A and B differential inputs have some sort hysteresis where this would not cause a problem.

 I am unsure if the transmitting transceiver we are using (SN65MLVD047) has a fast enough transition time from low to high and high to low.

can you please advise.

Thanks, best regards,

Klaus

  • Hi Klaus,

    What is the LVDS topology you are using here? If it is point to point I recommend using a driver like DS90LV011A. SN65LVDT14 does have some hysteresis but SN65MLVD047 may be a bit too slow in the worst case corners.   

  • Hi Malik, thanks for the reply. We tried measuring the waveforms on the bench with a differential probe in our slowest application. See below. This is the clock signal measured with a differential probe on the receiver IC’s pins (SN65LVDT14), the signal was driven by the SN65MLVD047 IC.

    You can see the transition from the max thresholds of SN65LVDT14 (+100 mV & -100 mV ) is about 74 nsec. Unless I am interpreting this wrong? Should it be +50mV --> -50mV giving a 100 mV swing, and vice versa? If that is the case, the transition time would be closer to 40 nsec.

    Do we know what the spec is for the receiver IC (SN65LVDT14)? Does this violate the transition times?

    Scopeshot

  • Hi Klaus,

    Rise time should be measured from 20% to 80% points on the edge. To my knowledge, there is not a specific input rise time spec for SN65LVDT14 however the general rule of thumb is that rise time should not be larger than 50% of the bit time as measured at the input of the receiver. In the at data rates higher than 100 Mbps SN65MLVD047 edge would be too slow (this also depends the transmission media).   

    Are you seeing a particular issue?