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DS90UB962-Q1: Error Handling, End of Frame discard

Ryan Wang
Expert 7445 points
Part Number: DS90UB962-Q1

Dear expert,

How to enforce UB962 does NOT drop end of frame even in error condition?

Customer use UB935+UB962. Randomly, UB962 drop end of frame continuously (for example, 5 successive End of Frame is missing) in real vehicle testing. This cause SoC video buffer overflow and hang up.

According to  datasheet 7.5.10 Error Handling,  PORT_CONFIG2 and PORT_PASS_CTL are all already clear to 0. But the problem is still there randomly.

Also tried to clear GENERAL_CFG Register RX_PARITY_CHECKER_EN to 0.  But the problem is still there randomly.

I don't quite understand CSI_WAIT_FS/CSI_WAIT_FS1 setting in PORT_CONFIG Register. Should I clear both bit to ensure NO packet is dropped at any error case? (PORT_CONFIG Register are in default value during test)

ECC_error and checksum error is inside CSI protocol, right? But Parity check is in FPD3 protocol, right?

For 30Hz frame rate,  5 successive End of Frame missing mean noise impact period is during 5*33ms=165ms period, correct?

If UB962 only has one FPD channel running, the problem seldom to happen. But with 2 or more FPD channel running, the problem happen frequently. Does this mean anything?

Is there any other register I can try or any other suggestion? 

Need your urgent help on this as the project is close to mass production.

Thanks

  • 0
    TI__Expert 7445 points

    BTW， I also have questions about PORT_CONFIG Register (Address 0x6D). Customer set this register to 0x7C

    Bit 2 is reserved and tagged as trap. What effect is customer set to 1 for this bit?

  • 0 in reply to Ryan Wang
    TI__Mastermind 18755 points

    Hi Ryan,

    Does this happen at all with only a single port running?  Can you select the ports in use and read back the VCID in register 0x72 and verify they are not overlapping.  It sounds initially like the CSI receiver is getting confused when simultaneous streams are coming in at the same time and is terminating them incorrectly.

    Regards,

    Nick

  • 0 in reply to Nicholas Darash
    TI__Expert 7445 points

    Nick,

    Thanks.

    The issue happen randomly. Seldom chance single port can happen as well.

    I will verify VCID.

    Could you also answer my other questions? I want to understand more about our silicon. I still doubt UB962 drop End of Frame at err condition.

  • 0 in reply to Ryan Wang
    TI__Mastermind 18755 points

    Hi Ryan,

    I don't think our device would drop end of frames for no reason, maybe try to share a reg dump so I can take a look but I think there may be an issue with SoC.  Are they able probe the CSI output of the 962 with a CSI analyzer?  

    As for your other questions I am not sure specifically what you want to know but if you set the pass control and port config to 0 then it should not truncate any packets on the CSI port.

    Regards,

    Nick

  • 0 in reply to Nicholas Darash
    TI__Expert 7445 points

    Nick,

    They are setting up equipment for CSI signal analyzer. Will keep you posted. 

    They are also dumping register as well. Will keep you posted. 

    Let me clarify my questions:

    1. CSI_WAIT_FS/CSI_WAIT_FS1. What is the effect of these two bits set to 1? If met some error, it will wait for new FS to receive packet? Before that, all packet are dropped?

    2.  ECC_error and checksum error is inside CSI protocol, right? But Parity check is in FPD3 protocol, right? 

    3. CSI package contain ECC and checksum for every line but not every frame, right?

    4. I want to calculate frequency of End of Frame. For 30Hz frame rate, it means End of Frame come at 30Hz rate, right?

    Thanks

  • 0 in reply to Ryan Wang
    TI__Mastermind 18755 points

    Hello,

    1. CSI_WAIT_FS will wait for a frame start packet prior to transmitting data. CSI_WAIT_FS1 will wait for at least one packet to be received with a frame count of 1 or greater.

    2. ECC_error and checksum errors are available inside the CSI packets.  FPD-Link uses parity to check for errors in the forward channel.

    3. CSI breaks each line into one long packet so yes its for line not frame.

    4. Yes, if you are operating at 30Hz then there should be 30 FE packets every second.  Also the 962 has an inter frame count register which could be useful for this.

    Regards,

    Nick

  • 0 in reply to Nicholas Darash
    TI__Expert 7445 points

    Nick，

    Thanks for feedback.

    For CSI_WAIT_FS=1, for example there is an error happen. Then UB962 will wait for a new FS prior to transmitting data? Or as far as UB962 has received one FS packet after power up, then it won't wait any more?

  • 0 in reply to Ryan Wang
    TI__Mastermind 18755 points

    Hello Ryan,

    If there is an error and the criteria is set such that it will truncate the frame, then yes it will wait for a new frame start.

    Regards,

    Nick