DS90UB948-Q1: How to connect the LVDS display

Hi Logan,

Thank you for the quick reply.

Best regards,

Niko

Hi Logan,

I now have the adapter PCB for the DS90UB948-Q1EVM.

I’m having problems getting a picture to my 2-port LVDS display (1920x1080) with the internal pattern generator of the ALP software (v.1.57.0010).

With a smaller 1-port LVDS display (800x480) everything works, the pattern generator draws pictures nicely. The 1-port display uses only the signals on the J15 of the EVM.

Switch S1 (MODE_SEL0) settings on the EVM:
- 2-port LVDS display: S1.5 on, all other switches off
- 1-port LVDS display: S1.7 on, all other switches off

ALP Setting for the 1080p display: Internal Timing, Spec: HD 1080p 60Hz

This is the only setting that gives me some kind of picture. With all the other setting I just get a black screen.

Any other fixed pattern than white or blue gives me a black screen. The white pattern gives kind of a white screen, but there is some interference running on the left edge, like this

The blue pattern gives a greenish screen with lots of interference running across the screen.

 

The 1080p display, or the LVDS cable are not broken. They work nicely with an HDMI-LVDS converter board. My adapter PCB has the same pinout as the HDMI-LVDS converter, so I’m using the same LVDS cable for both. I’ve now triple-checked the connections on my adapter board, so I don’t think this is a HW problem. And at least the odd channel works, as the 800x480 display is working. I measured the LVDS signals on the J15 and J16 connectors with an oscilloscope, with both displays. I didn’t notice any significant differences between them.

Do you have any idea what’s the problem here and how can I get the 2-port LVDS display working?

Best regards,

Niko

Hi Niko, 

Can you do a register dump of 948 during this condition? 

Can you also verify the color format of 948 matches what the panel expects? (MAP_SEL setting)

Regards, 

Logan

Hi Logan,

Here's the registers dump, while I'm driving the fixed white pattern to the display. Registers_dump.zip

If I've understood the datasheets correctly, MAPSEL should be high, as the MSBs seem to be on D3 & D7. I'm referring to Figure 7-17 of the DS90UB948-Q1 datasheet and the display datasheet chapter ‘3.4 LVDS Interface’, see below:

I’ve tried different settings with S1. I believe the S1.5 should be on, but the display behaves the same way, no matter which one of the switches is on: 1, 2, 5 or 6. By turning on any of the switches 3, 4, 7 or 8, I just get a black screen.

Here’s my ALP settings

Best regards,

Niko

Hi Niko, 

Thanks for the register dump, I'll review them and get back to you on Monday. 

One other thing, can you also attach the actual display timing parameters of the panel you are connecting to? 

Regards, 

Logan

Hi Logan,

Thanks for you help! Here’s the signal timing specification from the datasheet. The datasheet can be found here, if you need some other details:

https://www.data-modul.com/sites/default/files/products/EV156FHM-N11-specification-12047755.pdf

Best regards,

Niko

Hi Logan,

I noticed that the minimum pixel clock of the display is 100 MHz. Which is the maximum that the DS90UB948-Q1EVM can supply. Could it be that the EVM cannot quite deliver the minimum of 100 MHz, and that's the reason why the image is not synchronizing? If I set the pixel clock in ALP to lower than 100 MHz, I always get a black screen.

Regards,

Niko

Hi Niko, 

Niko Tarnanen said:

Could it be that the EVM cannot quite deliver the minimum of 100 MHz

This might be the case. As described in this application note on PatGen, the frame rate will vary while the video timing is forced. 

Are you able to set video from a SER with proper video timing, or use external CLK? 

Regards, 

Logan