DS90UB954-Q1: About I2S Evaluation when runs FPD-Link III 2Gbps line rate

Hi Chris,

There is not a specific table that can be referenced for 2Gbps, but some math can be done to derive the 2Gbps table. First, let me explain the 4Gbps table.

In 935/953 serializers that are not in DVP mode, the Forward Channel (FC) frame is 40-bits. A GPIO pin is sampled once every FC frame. Suppose you are using a 25MHz REFCLK in Synchronous mode, then the FC line rate is 4Gbps.

4Gbps / 40-bits per frame = 100MHz (Frames per second)

We recommend an oversampling of 4x the signal frequency, so the signal sampled at one of the GPIO pins is at most, 100MHz/4 = 25MHz.

If we want to sample 2 GPIO pins, then one frame will sample the first GPIO and then the next frame will sample the second GPIO, thus reducing the sampling frequency at each GPIO pin to half the frames per second rate.

I am not clear on what mode your application line rate is, but if you for example, operate in Non-Synchronous mode and use a 25MHz external reference clock for the serializer, then the FC line rate will be 2Gbps (See Table 7-6. Clocking Modes in the UB935 datasheet for more details).

In the case where 4 GPIO pins are being sampled, each GPIO is actually sampled every 5 FC frames because of the internal DCA scrambling and encoding sequence on the UB935. If the system is running a FC rate of 2Gbps and 4 GPIO pins are being sampled:

2Gbps / (40-bits per frame * 5 frames) = 10MHz (Sampling frequency)

Max frequency of signal sampled at GPIO pins = 10MHz/4 = 2.5MHz (x4 oversampling)

Best,

Justin Phan