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AM26C32: Channel to Channel Skew

Part Number: AM26C32

Hi Team, seeking some clarification.

What is the channel to channel skew of the part? It is not specified in the datasheet. Passing two signals through different channels on the same part that need to maintain a certain timing relationship to each other. 

Thank you.

-Mark

  • Hi Mark,

    Due to this being an older part + a spec we don't often spec in most of our Differential Transceivers we don't have an explicitly measured value for this parameter. This is typically because while this value is most likely not 0 - it is generally going to be small enough where it is negligible to the application itself.

    However we can make an educated guess on some general boundary conditions and the incoming signal data rate to judge whether or not this should be a problem.

    Ultimately channel to channel skew is going to be the the delta between single channel pulse skew between the various channels - which single channel pulse skew is the defined as |T_PHL - T_PLH| - or the magnitude of the difference between high to low and low to high propagation delays. 

    So with the specs with a 50pF loading capacitance this is where we are looking at for prop delays - the part is spec'd with symmetrical prop-delay times - which generally means the charge and discharge pathways have the same RLC components to them and more or less should be affected the same. Essentially the two largest components of this delay are going to be the input resistance and its capacitance. This capacitance is parasitic and while it may change with temp the larger change is going to come from the resistance versus temperature. Since all the channels are just copied cells  (with RX inputs shown below):

    Since the input resistance is variable with temperature (resistance will increase as temp increases) each channel should perform more or less the same under the same temperature conditions. 

    With all these factors considered it is unlikely that the skew value is > ~5ns if it even gets that high as they are symmetric prop-delays and the largest factor that will increase/decrease prop delays is temperature or loading capacitance (which very well may be lower than 50pF which would also lower prop delay) so at the same temperature you should be getting very little channel to channel skew. 

    Now this doesn't necessary work for every single application - but typically for the data-rates seen in RS-485 / RS-232 (what this part is build around) are not going to be fast enough where this small channel to channel skew is affecting functional properties of the bus.

    However to double check:

    What is the length of the bus and what is the desired data rate you are trying to achieve ? 

    Do you have any requirements on hold time for a bit before its considered "Valid" ? 

    What cable are you using between TX and RX (or just characteristic impedance)  + bus loading conditions

    Also if you know a temp range this will be used at will also help - as the max skew would most likely happen around max temperature - and the lower the temp the most likely the skew approaches 0. 

    With that information I should be able to confirm if this will work for the application - I think it should be fine, but there could be some outlier applications.

    Please let me know!

    Best,

    Parker Dodson