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DP83867IS: RGMII Timing

Noriyuki Takahashi
Genius 11020 points
Part Number: DP83867IS

Hi team

Customer wants to understand 7.10 RGMII Timing on the datasheet. Could you support?

1.  Do they need to create a PCB layout to meet 7.10 RGMII Timing? 

2. Does 7.10 RGMII Timing vary with VDDIO voltage (1.8V/2.5V/3.3V)?

3. Timings as below are for MAC interfaces? 
TskewT  Data to Clock output Skew (at Transmitter)

TsetupR Data to Clock input Setup (at Reciever – internal delay)

TholdR  Clock to Data input Hold (at Receiver – internal delay)

4.  Do these timings as below guarantee a setup and hold of 1.2ns(min) for delayed RXC rising/falling?

TsetupT Data to Clock output Setup (at Transmitter – internal delay)

TholdT  Clock to Data output Hold (at Transmitter – internal delay)

Regards,

Noriyuki Takahashi

  • 0
    TI__Expert 3727 points

    Hi Takahashi-san,

    1. The delay spec needs to be met for both the PHY as well as the MAC to guarantee operation. 

    2. The specs in datasheet, are for all VDDIOs, the timing doesn't vary with VDIOO

    3. These are on the PHY side. 

    4. Our usual method to make sure the timing is met, is to delay either transmitter or receiver, if you are delaying on receiver of PHY, then you may not delay TX mac side, and vise versa, one of them needs to be delayed and the RGMII timing can be checked to meet requirements in this condition.

    Best, 

    Alon

  • 0 in reply to Alon Kopelman
    TI__Genius 11020 points

    Alon,

    When they use the device at RGMII, 100Mbps and all same length of PCB traces, could you tell the recommended RGMII Receive Clock Delay and RGMII Transmit Clock Delay?

    Could you also explain how to calculate the delay time? 

    They need to decide the delay time but not sure how to decide the delay time. Please let me know if you need more information for the calucation.

    Regards,

    Noriyuki Takahashi

  • 0 in reply to Noriyuki Takahashi
    TI__Genius 11020 points

    Alon,

    Could you help this?

    Regards,

    Noriyuki Takahashi

  • 0 in reply to Noriyuki Takahashi
    TI__Expert 3727 points

    Hi Takahashi-san,

    Please view following image for recommended RGMII clock delay and criteria. 

    I am not sure what you mean by how to calculate the delay timing, if the specs above do not help with your query, please elaborate on what you mean by 'how to calculate delay time'. 

    In RGMII the clock has to be skewed in order for operation. 

    Best, 

    Alon

  • 0 in reply to Alon Kopelman
    TI__Genius 11020 points

    Alon

    I think customer needs to adjust the delay timining by RGMIIDCTL register to meet the recommended RGMII clock delay and criteria you showed.

    I am not sure how to decide the delay timing. I thought the delay timing can be caluclated. Could you give advice on this?

    Regards,

    Noriyuki Takahashi

  • +1 in reply to Noriyuki Takahashi
    TI__Expert 3727 points

    Hi Takahashi-san,

    I confirmed with the team, you do not need to calculate the clock delay, there are only a few clock delays which you can test, once you find the range of clock delays that work, test to see which one provides the best result. 

    I hope this helps. 

    Best,

    Alon