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SN65DSI86 color issue

george george
Prodigy 20 points
Other Parts Discussed in Thread: SN65DSI86

I refer to the content of Script_NoASSR to set SN65DSI86. But I still can't see the color bar
configuration as below

:/ # i2cdump -y 2 0x2c
0 1 2 3 4 5 6 7 8 9 a b c d e f
00: 36 38 49 53 44 20 20 20 02 00 82 00 00 01 00 00
10: 26 00 7c 7c 00 00 00 00 00 00 00 00 00 00 00 00
20: 80 07 00 00 38 04 00 00 00 00 00 00 30 00 00 00
30: 12 00 00 00 58 00 0b 00 18 00 03 00 12 00 00 00
40: 01 00 00 00 80 00 20 08 58 04 88 00 1d 00 30 00
50: 12 00 80 07 38 04 20 00 40 1b 0c 00 10 00 f0 00
60: a0 60 a4 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 01 02 00 80 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 1f 7c f0 c1 07 1f 7c
90: f0 c1 07 30 20 00 00 04 01 00 00 00 00 00 00 00
a0: 01 ff ff 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 04 78 ac ac 08 6c 9c 9c 0c 5c 5c 5c 0c 0c 0c 0c
c0: 3f 3f 0f 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 08 02 00 00 02 00 00 00 00 00 00 00

address 0x59 is 0x1b because we need to lanes swap

  • 0
    TI__Guru**** 176811 points

    Hi,

    Please see this e2e FAQ, https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945404/faq-sn65dsi86-how-do-i-programming-the-sn65dsi86-registers, have you used the spreadsheet in the e2e FAQ to generate the DSI86 registers programming values based on the EDID information?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 20 points

    Hi David,
    I create a shell script with reference to 2DP_4DSI_RBR_800x600_Color_Bar.xml
    The content of my script is as follows
    i2cset -fy 2 0x2c 0x5c 0x01 b
    i2cset -fy 2 0x2c 0xff 0x07 b
    sleep 0.2
    i2cset -fy 2 0x2c 0x16 0x01 b
    sleep 0.2
    i2cset -fy 2 0x2c 0xff 0x00 b
    i2cset -fy 2 0x2c 0x10 0x26 b
    i2cset -fy 2 0x2c 0x59 0x1b b     // for lanes swap
    i2cset -fy 2 0x2c 0x5A 0x04 b
    i2cset -fy 2 0x2c 0x93 0x20 b
    i2cset -fy 2 0x2c 0x94 0x20 b
    i2cset -fy 2 0x2c 0x95 0x00 b
    i2cset -fy 2 0x2c 0x0d 0x01 b
    sleep 1
    i2cset -fy 2 0x2c 0x96 0x0a b
    i2cset -fy 2 0x2c 0x20 0x00 b
    i2cset -fy 2 0x2c 0x21 0x04 b
    i2cset -fy 2 0x2c 0x24 0x58 b
    i2cset -fy 2 0x2c 0x25 0x02 b
    i2cset -fy 2 0x2c 0x28 0x00 b
    i2cset -fy 2 0x2c 0x29 0x00 b
    i2cset -fy 2 0x2c 0x2c 0x80 b
    i2cset -fy 2 0x2c 0x2d 0x80 b
    i2cset -fy 2 0x2c 0x30 0x04 b
    i2cset -fy 2 0x2c 0x31 0x80 b
    i2cset -fy 2 0x2c 0x34 0x28 b
    i2cset -fy 2 0x2c 0x36 0x09 b
    i2cset -fy 2 0x2c 0x38 0x28 b
    i2cset -fy 2 0x2c 0x3a 0x01 b
    i2cset -fy 2 0x2c 0x5b 0x01 b
    i2cset -fy 2 0x2c 0x3c 0x10 b
    i2cset -fy 2 0x2c 0x5a 0x0c b

    And I check that the value of 0xF8 is 0x02
    Am I missing something?

  • 0 in reply to george george
    TI__Guru 60870 points

    We will review and confirm next week.

    Regards,

    JMMN

  • 0 in reply to JMMN
    TI__Guru**** 176811 points

    Hi, 

    Status register 0xF8 returns a value of 0x02 would indicate link training failure on the eDP interface. Can you please share your schematic for review? Are you connecting to a regular DP monitor or a LCD panel? I would double the physical connection on the eDP first. 

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 20 points

    Hi David


    Now we can see the color bar. But we can not see picture from SOC DSI interface.
    I use the following command to configure the bridge IC.
    Am I missing something?


    i2cset -fy 3 0x2d 0x09 0x01 b
    i2cset -fy 3 0x2d 0xff 0x07 b
    i2cset -fy 3 0x2d 0x16 0x01 b
    i2cset -fy 3 0x2d 0xff 0x00 b
    i2cset -fy 3 0x2d 0x0a 0x06 b
    i2cset -fy 3 0x2d 0x10 0xa0 b
    i2cset -fy 3 0x2d 0x12 0x77 b
    i2cset -fy 3 0x2d 0x13 0x77 b
    i2cset -fy 3 0x2d 0x94 0xe0 b
    i2cset -fy 3 0x2d 0x0d 0x01 b
    i2cset -fy 3 0x2d 0x5a 0x04 b
    i2cset -fy 3 0x2d 0x93 0x30 b
    i2cset -fy 3 0x2d 0x96 0x0a b
    i2cset -fy 3 0x2d 0x20 0x80 b
    i2cset -fy 3 0x2d 0x21 0x07 b
    i2cset -fy 3 0x2d 0x22 0x80 b
    i2cset -fy 3 0x2d 0x23 0x07 b
    i2cset -fy 3 0x2d 0x24 0x70 b
    i2cset -fy 3 0x2d 0x25 0x08 b
    i2cset -fy 3 0x2d 0x2c 0x20 b
    i2cset -fy 3 0x2d 0x2d 0x00 b
    i2cset -fy 3 0x2d 0x30 0x05 b
    i2cset -fy 3 0x2d 0x31 0x00 b
    i2cset -fy 3 0x2d 0x34 0x50 b
    i2cset -fy 3 0x2d 0x36 0x36 b
    i2cset -fy 3 0x2d 0x38 0x30 b
    i2cset -fy 3 0x2d 0x3a 0x03 b
    i2cset -fy 3 0x2d 0x5b 0x00 b
    i2cset -fy 3 0x2d 0x5a 0x0c b
    i2cset -fy 3 0x2d 0x59 0xe4 b
    i2cset -fy 3 0x2d 0x93 0x20 b

    Thanks

  • 0 in reply to george george
    TI__Guru**** 176811 points

    Hi,

    Please see this e2e FAQ debugging guide, https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945403/faq-sn65dsi86-sn65dsi86-black-screen-debugging-guide.

    Can you clear and then dump out status registers 0xF0 to 0xF8?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 20 points

    Hi David,
    I write 0xFF to register 0xF0 ~ 0xF8 and then read 0xF0 ~ 0XF8.
    The values as follows.

    0xF0->0x00
    0xF1->0x00
    0xF2->0x00
    0xF3->0x00
    0xF4->0x00
    0xF5->0x01
    0xF6->0x00
    0xF7->0x00
    0xF8->0x00

    Thanks

  • 0 in reply to george george
    TI__Guru**** 176811 points

    Hi,

    Can you send their schematic, layout, and the panel EDID information?

    Can they also map the DSI HSYNC and VSYNC to the DSI86 GPIO using register 0x5F and measure the DSI HYSNC and VSYNC frequency?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 20 points

    Hi David,
    We are now using sn64dsi86 demo board and MTK MT2715. We just connect DSI interface and i2c interface.
    DP monitor is acer CB280HK and EDID as follows.
    00,FF,FF,FF,FF,FF,FF,00,04,72,0A,04,1F,36,50,64,2D,1A,01,04,A5,3E,22,78,3E,08,A5,A2,57,4F,A2,28,
    0F,50,54,BF,EF,80,81,C0,81,00,81,80,95,00,B3,00,81,40,D1,C0,71,4F,4D,D0,00,A0,F0,70,3E,80,30,20,
    35,00,6D,55,21,00,00,1A,04,74,00,30,F2,70,5A,80,B0,58,8A,00,6D,55,21,00,00,1A,00,00,00,FD,00,17,
    50,1E,A0,3C,01,0A,20,20,20,20,20,20,00,00,00,FC,00,41,63,65,72,20,43,42,32,38,30,48,4B,0A,01,68

    Thanks

  • 0 in reply to george george
    Prodigy 20 points

    Hi David,
    Do you have any ideas?

  • 0 in reply to george george
    TI__Guru**** 176811 points

    Hi,

    The EDID shows the pixel clock to be 533.25MHz. 

    To support pixel clock of 533.25MHz, 

    Assume BPP = 18, and looking at the register value, they are only using DSI Channel A.

    DSI Clock Frequency = 533.25*18 / 4 * 2 = 1199.8125MHz which is outside the DSI86 DSI clock supported range. 

    So you have to use both DSI Channel A and B to support this monitor

    DSI Clock Frequency = 533.25*18 / 8 * 2 = 599.90625MHz which is inside the DSI86 DSI clock supported range. 

    They also have to use RGB666 (18bpp) because RGB888 (24bpp) will push the DSI clock out of the supported range.

    Have they used this spreadsheet to generate the DSI86 register programming value, https://e2e.ti.com/support/interface-group/interface/f/interface-forum/945404/faq-sn65dsi86-how-do-i-programming-the-sn65dsi86-registers

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 20 points

    Hi 
    I have change DSI to dual channel mode but it is still black screen.
    Am I missing something?
    The setting are as follows
    i2cset -fy 2 0x2c 0xff 0x07 b
    i2cset -fy 2 0x2c 0x16 0x01 b
    i2cset -fy 2 0x2c 0xff 0x00 b
    i2cset -fy 2 0x2c 0x0a 0x06 b
    i2cset -fy 2 0x2c 0x10 0x00 b
    i2cset -fy 2 0x2c 0x59 0x1b b
    i2cset -fy 2 0x2c 0x12 0x77 b
    i2cset -fy 2 0x2c 0x13 0x77 b
    i2cset -fy 2 0x2c 0x94 0xE0 b
    i2cset -fy 2 0x2c 0x0D 0x01 b
    i2cset -fy 2 0x2c 0x5A 0x04 b
    i2cset -fy 2 0x2c 0x93 0x30 b
    i2cset -fy 2 0x2c 0x96 0x0A b
    i2cset -fy 2 0x2c 0x20 0x80 b
    i2cset -fy 2 0x2c 0x21 0x07 b
    i2cset -fy 2 0x2c 0x22 0x80 b
    i2cset -fy 2 0x2c 0x23 0x07 b
    i2cset -fy 2 0x2c 0x24 0x70 b
    i2cset -fy 2 0x2c 0x25 0x08 b
    i2cset -fy 2 0x2c 0x2C 0x20 b
    i2cset -fy 2 0x2c 0x2D 0x00 b
    i2cset -fy 2 0x2c 0x30 0x05 b
    i2cset -fy 2 0x2c 0x31 0x00 b
    i2cset -fy 2 0x2c 0x34 0x50 b
    i2cset -fy 2 0x2c 0x36 0x36 b
    i2cset -fy 2 0x2c 0x38 0x30 b
    i2cset -fy 2 0x2c 0x3A 0x03 b
    i2cset -fy 2 0x2c 0x5B 0x00 b
    i2cset -fy 2 0x2c 0x5A 0x0C b

    Thanks

  • 0 in reply to george george
    TI__Guru**** 176811 points

    Hi,

    The video timing registers values now look correct, but why do you program register 0x59 with the value of 0x1B, does this match your DP lane implementation? 

    To support this resolution, the DSI source has to send RGB666 with ~600MHz DSI clock, are you doing that?

    Can you also map the DSI HSYNC and VSYNC to the DSI86 GPIO using register 0x5F and measure the DSI HYSNC and VSYNC frequency?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 125 points

    Hi David:

    If i use this command script as list

    i2cset -fy 2 0x2c 0xff 0x07 b
    i2cset -fy 2 0x2c 0x16 0x01 b
    i2cset -fy 2 0x2c 0xff 0x00 b
    i2cset -fy 2 0x2c 0x0a 0x06 b
    i2cset -fy 2 0x2c 0x10 0xa0 b
    i2cset -fy 2 0x2c 0x59 0x1b b
    i2cset -fy 2 0x2c 0x12 0x77 b
    i2cset -fy 2 0x2c 0x13 0x77 b
    i2cset -fy 2 0x2c 0x94 0x80 b
    i2cset -fy 2 0x2c 0x0D 0x01 b
    i2cset -fy 2 0x2c 0x5A 0x04 b
    i2cset -fy 2 0x2c 0x93 0x30 b
    i2cset -fy 2 0x2c 0x96 0x0A b
    i2cset -fy 2 0x2c 0x20 0x80 b
    i2cset -fy 2 0x2c 0x21 0x07 b
    i2cset -fy 2 0x2c 0x22 0x80 b
    i2cset -fy 2 0x2c 0x23 0x07 b
    i2cset -fy 2 0x2c 0x24 0x70 b
    i2cset -fy 2 0x2c 0x25 0x08 b
    i2cset -fy 2 0x2c 0x2C 0x20 b
    i2cset -fy 2 0x2c 0x2D 0x00 b
    i2cset -fy 2 0x2c 0x30 0x05 b
    i2cset -fy 2 0x2c 0x31 0x00 b
    i2cset -fy 2 0x2c 0x34 0x50 b
    i2cset -fy 2 0x2c 0x36 0x36 b
    i2cset -fy 2 0x2c 0x38 0x30 b
    i2cset -fy 2 0x2c 0x3A 0x03 b
    i2cset -fy 2 0x2c 0x5f 0xeb b
    i2cset -fy 2 0x2c 0x5B 0x01 b
    i2cset -fy 2 0x2c 0x3c 0x00 b
    i2cset -fy 2 0x2c 0x5A 0x0C b
    i2cset -fy 2 0x2c 0x96 0x01 b
    i2cset -fy 2 0x2c 0x93 0x30 b

    and check gpio 2&3 H or Vsync frequence is 117Khz

    but DP monitor always no display

    Other question:

    If i modify edid data (1920*1080)whcih don't match with DP connected monitor (3840*2160), and setup as previous script is ok?

  • 0 in reply to Wayne Lin
    Prodigy 125 points

    Hi David:

    How to set parameter 

    If i use 3840*1920 EDID. Pixel clock is 533,Mhz, streamBitRate= 533*18 (RBG666)=9.594Gbps (in)

    eDP Total Bit Rate = #_of_eDP_Lanes × DataRate × 0.80= 4 × 2.7 Gbps ((HBR)× 0.80 = 8.64Gbps (out)

    input is over output.

    Then other HW DSI lane schematic is only used DSIA without DSIB.

    So it means i can't use 4K2K monitor to test right?

  • 0 in reply to Wayne Lin
    TI__Guru**** 176811 points

    Hi,

    So if number of DSI_Lane = 4, then DSI_CLK_FREQ = 9.594 / 8 = 1199.25MHz, outside the max supported frequency of 750MHz.

    With DSI_Lane = 8, then DSI_CLK_FREQ = 599.625MHz.

    So you have to use both DSIA and DSIB to support this resolution.

    Thanks
    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 125 points

    Hi David:

    Sorry, I check Ti SN65DSI86 datasheet, it write this key words in 9.2.1.2.3 DSI Design Procedure (70 page)

    "Because the SN65DSI86 can support a DSI clock rate of up to 750 MHz (or 1.5 Gbps)".

    I don't know how to change with 1.5Gbps? 

  • 0 in reply to Wayne Lin
    TI__Guru**** 176811 points

    Hi,

    750MHz is the maximum clock frequency DSI86 can support. 

    If you want to drive 1.5Gbps, then you have to configure it through the DSI source.

    Thanks

    David