Other Parts Discussed in Thread: DP83869
Our project uses the DP83869 chip in RGMII-SGMII mode. The block diagram is shown in the figure.
The RGMII interface is connected to the MAC of the LS1027 (NXP) processor.
The SGMII interface is connected to the VSC8552 chip (PHY MICROCHIP). We were unable to get the DP83869 to work in Autonegotation mode.
We took the advice from (https://e2e.ti.com/support/interface-group/interface/f/interface-forum/911770/dp83869hm-bridge-rgmii-to-sgmii-mac-to-mac-configuration/3385960?tisearch=e2e-sitesearch&keymatch=DP83869%2520RGMII%2520to%2520SGMII#3385960).
We have written to the register REG(0xC00) = 0x0140. After that, the above block diagram started working in 1G mode. Throughput tests at 1G pass without comment. Now we needed to conduct similar tests in 100M mode. To do this, write to the register REG (0xC00) = 0x2100.
However, the Ethernet packets are not getting through. All necessary signals are present on the RGMII DP83869 interface pins. Activity is visible on the RX_D[0:3], RX_CTRL/RX_DV lines. There is a 25MHz clock signal on the RX_CLK pin.
However, the ethtool utility (which is running on the LS1027 processor) shows that fragmented frames are arriving on the MAC interface. manipulations with the fields DLL_RX_DELAY_CTRL_SL and DLL_TX_DELAY_CTRL_SL of the ANA_RGMII_DLL_CTRL Register (Address = 0x86) do not change the situation.
Has the DP83869 been configured correctly?