TUSB564: DPEQ setting by I2C and symbol lock

Hardy

Equalization setting # matches with the DQEQ level. For example, if you write 0x55 to register 0x10 and 0x11, then 6.5dB equalization of DPEQ is applied.

Please make sure register 0x0A bit  4 is set so EQ settings based on programmed value of each of the EQ registers.

Thanks

David

Hi David,

Thanks for your comment.

1. The connection block as below. What EQ level would you suggest to set? If this value still cannot symbol lock, should we try to enhance EQ level?

2. For RX measurement, do we need additional tool to do compliance?

Best regards,

Hardy

Hardy

How long is the trace between the TUSB564 and The USBC conn? The DPEQ should be set to compensate for the loss between the USBC conn and the TUSB564. 

For the RX test, they need to make sure the link training is successful before starting the RX JTOL test.

Thanks
David

Hi David,

Update trace length information as below picture. Could you comment what EQ level we can try and if there is any formula we can estimate approximate loss such as 1inch/0.5db@5Gbps?

Best regards,

Hardy

Hardy

Please see this link on estimate the trace insertion loss, https://www.edn.com/loss-in-a-channel-rule-of-thumb-9/. And base on the estimated loss, you can set the corresponding TUSB564 EQ value.

Thanks

David