Hi Ti engineer,
1. What is the difference between FAULTRES and NRESET? When to use FAULTRES and when to use NRESET?
2. How to use FAULTRES and NRESET? FAULTRES, NRESET Low active? What is the minimum duration of low level? Recommended reduction time?
3. If PGA411 needs to be reset during power-on, how should the timing be handled?
4.After power-on initialization, both the main chip and PGA411 have completed the reset self-check. Can the reset times be increased? Is there any harm in that?
Ian,
The NRESET is used on power-on reset. When it is LOW (DGND)
You can see this in the state diagram on page 47 of the data sheet:
When the NRESET pin is low (DGND), the PGA411-Q1 logic is frozen and the device is in the RESET state and the
PGA411-Q1 logic is frozen and the device is in the RESET state. When the NRESET pin is pulled up, the logic is
enabled after a 70-μs deglitch period and the device is operational. See section 7.4.1 of the data sheet for more information.
If a FAULT that occurs during normal operation drives the the device to the FAULT state, and the FAULTs are subsequently cleared, the FAULTRES pin can be toggled (HIGH-LOW-HIGH) to transition the device back to normal operation. See section 7.4.4 of the data sheet for more information.
Timings are shown in Figure 6-2 of the data sheet.
Regards,
John
