Hi Team,
Customer wants to know what's the detailed test condition for I2C input rise time? I cannot find it in our D/S, pls help us look at this. Thanks.
Best,
Stanley
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Hi Team,
Customer wants to know what's the detailed test condition for I2C input rise time? I cannot find it in our D/S, pls help us look at this. Thanks.
Best,
Stanley
These values are simply copied from the I²C specification. There are no fixed test conditions; these timings must be met by the actual circuit.
The specification also says this about the fall time:
[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.
Hi Clemens,
Thanks for comments. Do you know what's typical voltage range we will take for estimating this rise/fall time? Like 20%-80% of voltage?
Best,
Stanley