Other Parts Discussed in Thread: AM6526,
In an application using the AM6526 and DP83867IS, the AM6526 SR2.1 Datasheet requires a Slew Rate within 2.65～5V/ns.
From this E2E post, this requirement comes from a JEDEC spec, not the limitations of the AM6526 MAC.
The following signals have been measured to confirm Slew Rate:
RX_CLK
RX_CTRL
RX_D[3:0]
The measured Slew Rate was 1.27～1.67V/ns.
Is there any setting that can be used to increase the drive strength of these signals?
At this stage in the design, there is no way a board layout revision can be made...
(Devices are only 1cm away, and trace lengths are around 33mm only)
