Hi Team,
Is there a Schmitt trigger inside the SMB of TCA9555?
Best regards,
Hardy
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I'm not sure what you mean by SMB but the SDA/SCL of our I2C target devices use CMOS inputs with minor hysteresis. Afterwhich, we filter the signal as required by I2C spec for 50 ns deglitch (again only I2C target devices have this and requrie this).
-Bobby
Hi Bobby,
We detected a unsolvable non-monotonic waveform when we tested SMB CLK signal at TCA9555PWR(write mode, write from BMC to TCA9555PWR with a long-open cable). So customer would like to know if TCA9555PWR CLK pin design with Schmitt trigger.
Best regards,
Hardy
That step in the signal is likely from a Pass-FET on the I2C bus. I'm willing to bet your system has some kind of pass FET level shifter or I2C switch/mux causing the short step on the signal. Since it seems like your fall time is stated to be ~23ns, the step is likely short and lower than the 50ns so this shouldn't cause issues in an I2C bus (or our device).
-Bobby