Hi team,
we are using DS90UB949 in the design, I am aware there is SSC clock in the DS90UB949. Our processor has some default SSC settings. I want to know, Is it within the limit or not?
we have two-stage of SSC output. PLL --> SoC --> Serializer (949)
PLL SSC profile :
PLL output 35MHz :
Consider the center spread is 2.5% and down spread is 2.5% for modulation frequency of 60KHz
Processor SSC profile :
Fmod : 0.03MHz / mode = downspread (-3%)
Consider the pixel clock is 113MHz.
DS90UB949 profile :
Is this fine to keep SSC on PLL and SoC or it will impact the serializer performance. ?
Can I disable the PLL SSC and keep the SoC Spread?
Thanks,
Selva S