Other Parts Discussed in Thread: DP83869
Hi,
I am using DP83869 Phy along with Artix 7 FPGA . The LAN is not communicating with the PC. The IC is configured in MII mode. The Tx Clock is having only 100mV swing. The details are given below.
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The DP83869 is used in MII mode.
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VDDIO voltage used is 3.3V and the IC is used in 2 supply mode. 1.8V supply is not connected.
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MDIO is pulled up with 2.5k ohm resistor
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The voltage at 11k Rbias resistor is 1V
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After power up the reset is held low for 201ms
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Then the registers are configured as follows:
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0x01DF0060
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0x00005100 (10 Mbps MII loopback)
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0x00105048
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0x00090800
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The registers are written with 34 clock cycles with first and last bit as high impedance.
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Once programmed I am getting Rx clock as 2.5 MHz with 3.3V (Pk-Pk). Tx Clock is 2.5 MHz but swing is only 100mV.
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When connected to PC the link is not getting through.
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When checked at the output of the magnetics, 10Base-Te Link Pulse is detected. Auto-Negotiation FLP is also detected. Screenshots of Link pulse and FLP attached.
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The LAN connector used on the PCB is a circular connector, 801-023-07M7-10SA (Mighty Mouse). One end of the LAN cable has the mating connector for the circular connector and the other end of the cable is an RJ45 connector which is connected to the PC. The connection from circular connector to RJ45 is as per the attached wiring diagram recommended for 568B.
Phy Circuit Diagram:
Magnetics Schematic:
Phy Tx Clock:
Phy Rx Clock:
Phy Output Clock:
Link Pulse:
Auto Neg FLP:
Kindly let me know whether I am missing anything in the design.
Thanks & Regards,
Shafna