TFP401A: the state of QE/QO-pins when Rx-pins are open

Noriyuki-san:

    This ticket was assigned and will response soon.

Regards

brian

Noriyuki-san

Are they pulled PDO low? Pulling PDO low places all the output drivers, except CTL1 and SCDT, into a high-impedance state.

An internal pullup on the PDO pin defaults the TFP401/401A to the normal non power-down output drive mode if left unconnected.

Thanks

David

David,

PDO is pulled up by 3.3V with 10kOhm. Do you mean that they should pull PDO-pin low to prevent  the uncertain state of QE/QO-pins?

They want to prevent that the state of QE/QO-pins are uncertain, becasuse the uncertain state can damage the device that is connected with QE/QO-pins. Are their any comments on this?

Regards,

Noriyuki Takahashi

Noriyuki-san

Pulling PDO down would put the output drivers into power-down state. During output drive power down state, the output drivers (except SCDT and CTL1) are driven to a high-impedance state.

You can tie SCDT externally to PDO to power down the output drivers when the link is inactive.

Thanks

David

David,

Please let me make sure again.

1. Customer understands that the state of QE/QO-pins become the indefinite output when Rx-pins are open. Is this the indefinite output described in the datasheet as the known behavior?

The FPGA connected to QE/QO-pins can receive the the indefinite signals and work unexpectedly. 

2. If QE/QO-pins enter in the power-donw mode, are the outputs fixed to Low or High level?  They would like to know how to solve

David (ASIC) Liu said:

Pulling PDO down would put the output drivers into power-down state.

They would like to know how to solve that FPGA can recieve the indefinite signals and work unexpectedly.

Regards,

Noriyuki Takahashi 

Noriyuki-san

Have they tried to pull the PDO low and see the FPGA can correctly receive the signal?

Thanks

David 

David,

Not yet. They want to confirm these questions in advance.

Regards,

Noriyuki Takahashi