SN65LVDS100: phase noise for SN65LVDS100

assaf matia

Part Number: SN65LVDS100
Other Parts Discussed in Thread: CDCLVD2102,

Hi,

I want to use this device for buffering a clock toward FPGA that have also phase noise input requirements (dbc values at several frequencies).

do you have a phase noise graph results for this device ? (like you placed in the datasheet for CDCLVD2102 device for example).

thanks

over 3 years ago

0 David (ASIC) Liu over 3 years ago

TI__Guru**** 164981 points

Hi,

Please see section 10.3.2.1 Signaling Rate, Edge Rate, and Added Jitter, the nominal total jitter for the SN65LVDT10x family devices is 28 ps, while the worst case jitter is 65 ps. The 28 ps represents less than 6% of the UI and the 65 ps represents 13% of the UI.

Thanks

David