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TUSB1310 RX_ELECIDLE always low

Jasper Chen
Prodigy 30 points

I am developing U3 link layer myself by Xilinx FPGA.

The RX_ELECIDLE is always low after PHY_RESETN is de-asserted.

I think it as a warm reset so I can't exit Rx.Detect.Reset of LTSSM if the warm reset is not de-asserted.

I see the Errata of TUSB1301 about "RX_ELECIDLE low (it should be high) when not receiving a valid LFPS."

Could you give me some way for the problem?

  • 0
    TI__Intellectual 2995 points

    Jasper,

    The errata related to rxelecidle is for distinguishing lfps from SS signaling when powerdown==P0. It should not be a problem at reset. There must be some other problem causing rxelecidle to stay low. Anyway, our workaround for P0 is to gate rxelecidle with rxvalid, such that lfps is true when rxelecidle and rxvalid are both low.

  • 0 in reply to Wes Ray
    Prodigy 30 points

    The rxelecilde is toggled normally after I reset my U3 host.

    Now I go on LTSSM to receiver detection by power_down[1:0]=2'h2, tx_detrx_lpbk=1 and tx_elecidle=1.

    Then I wait phy_status asserted and check rx_status[2:0], but the phy_status is never asserted.

    Even I switch power_down[1:0]=2'h0, the phy_status is also not asserted.

    The phy_status only asserted during reset assertion.

  • 0 in reply to Jasper Chen
    TI__Intellectual 2995 points

    This isn’t much to go on for analysis.

    Did you wait for phystatus to go low before attempting receiver detection?

    Did you check vbus first?

    Is the phy properly configured for USB?

    Do you have the clocks hooked up properly?

    Do you have sync flops on the PIPE, but excluding phystatus, since it can be asynchronous during P3?

    We have implemented both USB host and device controllers with the 1310/1310A and we know of no issues with implementing the LTSSM.  Most likely this is an issue with the IP in the FPGA.

  • 0 in reply to Wes Ray
    TI__Mastermind 27890 points

    Closing for inactivity.