DP83867IRPAP-EVM: DP83867IRPAP-EVM

Hi Yashash,

Thank you for getting in touch with us.

Can you please let me know the following?

1. In which mode is RGMII configured on DP83867? Align mode or Shift/Internal delay mode?
2. Please check the same for the MAC Processor too.
3. Please share pictures/block diagram of the whole setup.

--
Regards,
Gokul.

Hi Gopal,

1.Phy mode configured is "rgmii-txid"
internal delay values are "DP83867_RGMIIDCTL_4_00_NS"file:///C:/Users/yashash/Desktop/Screenshot%202022-03-15%20154629.png
fifo depth value is "DP83867_PHYCR_FIFO_DEPTH_4_B_NIB"

complete Device tree entry is as shown below:

&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rgmii-txid";
phy-handle = <&ethphy1>;
phy-reset-gpios = <&lsio_gpio3 7 GPIO_ACTIVE_LOW>;
phy-reset-post-delay = <195>;
phy-reset-duration = <1>;
fsl,magic-packet;
nvmem-cells = <&fec_mac1>;
nvmem-cell-names = "mac-address";
fsl,rgmii_rxc_dly;
fsl,mii-exclusive;
status = "okay";

mdio {
#address-cells = <1>;
#size-cells = <0>;

ethphy1: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c22";
ti,rx-internal-delay = <DP83867_RGMIIDCTL_4_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_4_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance;
ti,dp83867-rxctrl-strap-quirk;
};
};
};

3.

With Regards,
Yashash

Hi Yashash,

The snapshot is missing in your message 'file:///C:/Users/yashash/Desktop/Screenshot%202022-03-15%20154629.png'. Can you please share the same?

What is the link speed for which you see these failures?

Also, please let me know the meaning of the terms 'DP83867_RGMIIDCTL_4_00_NS', 'DP83867_PHYCR_FIFO_DEPTH_4_B_NIB'.

Can you also let me know the routing length of RGMII signals between TI EVM and i.MX8 QM SOM? What are the estimated parasitic capacitance on these routings?

--
Regards,
Gokul.

Hi Gopal,

We are getting failures for all link speeds 10, 100 and 1000Mbps
*DP83867_RGMIIDCTL_4_00_NS means delay of 4 nano seconds
*DP83867_PHYCR_FIFO_DEPTH_4_B_NIB this is tx fifo depth value is 4 bytes/nibbles

With Regards,
Yashash

Hi Yashash,

The routings of the RGMII lines are a but higher than the recommended routing length of 5000 mils.

But the failure in 10M and 100M suggests that the issue is elsewhere.

One more thing I have observed is the wrong delay used for RGMII delay. 1G RGMII dictates that the skew between the clock and data is typically 2ns and not 4ns. Can you please try changing the RGMII TX delay to 2ns and verifying it?

Also, looks like PHY RX_Data lines are also skewed. This means that the processor has to sample the RX_Data in align mode.
Please check with the processor vendor on what is the skew they are expecting between clock and data. Configure the delay of the RX lines accordingly.

--
Regards,
Gokul.

Hi Gokul,
We have configured RGMII TX delay to 2ns and checked iMX8QM datasheet skew they are expecting 2.6 nano seconds between clock and data is, so we tried RGMII RX delay value as 2.5 and 2.75 nano seconds.
With this configuration rx_crc errors were not seen, but IP is not getting assigned.
Is there any extra configuration which needs to be done?

Regards,
Yashash

Hi Yashash,

It is good that we don't have CRC errors anymore. The IP assignment happens at MAC and higher levels. The PHY is not involved in this.

Can you please check with the processor vendor how the IP assignment happens? If they point it to the PHY, then we can look into the issue again.

Please let me know if you need more details.

--
Regards,
Gokul.