In our new design, we are using DP83867IS as 1G PHY,
The PHY is connected with Xilinx RFSoC GTR bank as SGMII, for our test purpose we need to check RGMII also, is possible to connect RGMII and SGMII pins at a time from the PHY to RFSoC, our preference is SGMII and RGMII for only some testing purpose. we are using one interface at a time, another interface is isolated, please find the attached image for clarification.
1. All the multiplexed signal the capacitor(0.1uF) and the resistor(22E) are in tripad mode to avoid stubs.
2. During SGMII mode the capacitor will mount and resistor do not mount and all other RGMII pins are isolated
3. During RGMII mode the resistor will mount and capacitor is no mount
4. MDC,MDIO pins are connected to PS
Could you please help us to confirm this configuration while RGMII/SGMII mode.
