XIO2001: Power-Up and Power-Down of 1.5V/3.3V/PCIR - Part2

Darren (FAE)

Part Number: XIO2001

It looks like following the EVM design will result in PCIR coming down about the same time as the 3.3V rail.
The User Guide for the EVM (p10) was referenced to show how PCIR could be implemented.

It uses an RC Filter from VDD_33 to PCIR, so PCIR comes up just slightly after 3.3V rails.
But that means during power-down, PCIR comes down slightly after the 3.3V rail.

Yet in the PowerDown sequence, it recommends, and Malik corroborated in the above E2E post, PCIR should be removed first...

During power-down, removing PCIR before 1.5V/3.3V is required to ensure that I/O cells of XIO2001 PCI bus are "OFF" then main power can be ramped down.

This contradicts the EVM setup...Could I get some clarification?
Should following the EVM setup, with PCIR connected to 3.3V rail using the RC filter be fine?

PCIR comes up slightly after 3.3V rail, and powers down slightly after 3.3V goes down...
this affect is minimized by selecting the proper RC time constant relative to the 3.3V rail's ramp rate...

Regards,
Darren

over 3 years ago

0 Nasser Mohammadi over 3 years ago

TI__Guru* 93570 points

Hi Darren,

I read through Malik's response and understand the discussion. Malik will be back next week and can make further comments. My thought is that following EVM - PCIR delayed version of VDD_33 - should be ok. I am thinking RC time constant of the delayed version does not allow in-rush current of VDD_33 to interact. Further if indeed there was an issue we would have known by now. Optimum solution is to make VDD_33 a delayed version of the PCIR 3.3V. However, this could make power supply design more complicated - especially given the fact we need to use a series R with PCIR.

Regards,,Nasser

0 Darren (FAE) over 3 years ago in reply to Nasser Mohammadi

TI__Expert 5483 points

Hi Nasser,

Appreciate you checking, thanks.
I'll wait further feedback next week then.

The customer is doing an implementation similar to the EVM, where PCIR basically tracks the VDD_33 rail.
Hopefully the comment from Malik is following the EVM design should be fine...

Regards,
Darren

0 Nasser Mohammadi over 3 years ago in reply to Darren (FAE)

TI__Guru* 93570 points

Hi Darren,

Just sent internal email asking for Malik's response when he comes back next week toward mi to end of next week. Please send me email so we can follow up with him.

Regards,,Nasser

0 Darren (FAE) over 3 years ago in reply to Nasser Mohammadi

TI__Expert 5483 points

Hi Nasser,

Has there been any update here...?

0 Nasser Mohammadi over 3 years ago in reply to Darren (FAE)

TI__Guru* 93570 points

Hi Darren,

Just checked with Malik and he will comment shortly.

Regards,,Nasser

0 Nasser Mohammadi over 3 years ago in reply to Nasser Mohammadi

TI__Guru* 93570 points

Hi Darren,

Malik is on vacation through this week and should be able to respond by early next week.

Regards,Nasser

+1 Malik Barton57 over 3 years ago in reply to Nasser Mohammadi

TI__Guru 64326 points

Hi Darren,

PCIR tracking VDD_33 should sufficient. The main goal here would to keep the the time where PCIR is "ON" and VDD_33 is "OFF" as small as possible. RC time constant is important here as you mentioned. As Nasser mentioned the optimum solution is to have PCIR to ramp down before VDD_33.

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XIO2001: Power-Up and Power-Down of 1.5V/3.3V/PCIR - Part2